RISC-V International, the nonprofit at the helm of the free and open-source CPU instruction set architecture, says it is writing a high-performance computing (HPC) roadmap of "new features and capabilities."
For an architecture which only began life at the University of California, Berkeley, in 2010, RISC-V has enjoyed considerable success.
A wealth of products based on RISC-V are already in the market, with more arriving regularly, but the majority of these, like Seagate's storage processor designs and the OpenTitan root-of-trust (RoT), target embedded or otherwise less performance-critical applications.
RISC-V International, though, believes there are more strings to its bow. In an announcement from member Dr John D Davis, chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC), it has set out its stall for taking over the performance end of the market.
"HPC is everywhere," claimed Davis. "The basic algorithms and kernels power a wide range of computations. It starts in the traditional space of supercomputers used for weather forecasting, computational fluid dynamics, to material science, and protein folding, in both research and industrial applications. We even see HPC in the cloud.
"The SIG-HPC aims to enable all of those workloads and more. As a result, there are 141 members on the mailing list and 10 active research, academia, and industrial members from a wide range of organisations and these are growing exponentially. The group is united in making RISC-V an option in HPC. It also works with other technical groups in RISC-V to make sure HPC requirements are kept in mind for the evolving ISA."
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While not committing to a formal roadmap, merely confirming one is in the works, Davis has set out the goals the SIG-HPC is targeting for the year ahead – beginning with an effort to map the exiting HPC software ecosystem to RISC-V. "This," he explained, "involves automation to discover which open source software, from libraries to benchmarks and applications, work out-of-the-box on the RISC-V ISA.
"Overall, SIG-HPC's vision is that of a future where the entire HPC system can be based on open source components. Today's technology trends require specialisation to meet the power and performance workload targets. This enables hardware-software co-design, which is a natural fit for open systems, enabling more research and development. The next major milestone for SIG-HPC is to map the HPC ecosystem and develop an associated roadmap."
It's not pie in the sky – back in 2019 Chinese tech giant Alibaba unveiled high-performance 16-core RISC-V chips for its cloud business. These, however, are proprietary, closed-source designs enabled by the permissive licensing behind the free and open-source RISC-V ISA itself, but of little use to a community looking to further the HPC effort.
That's not to say others aren't working on more open designs. In India the SHAKTI project, launched in 2014 by the Reconfigurable Intelligent Systems Engineering (RISE) Group of IIT-Madras, aims to produce open-source chip designs ranging from low-power E-Class parts for embedded machines up to H-Class for HPC – although it's early days yet.
"It is a very interesting ambition of the RISC-V community, which highlights that RISC-V can be competitive even beyond embedded and single-board computers," commented Philipp Wagner, director at the nonprofit FOSSi Foundation, which aims to build a community and ecosystem of free and open-source silicon including but not limited to RISC-V.
"There is a long road ahead, in particular for open-source silicon components to become integral parts of high-performance computing systems, and the creation of an enabling ecosystem is an important milestone."
In the meantime, SIG-HPC is actively soliciting new members to assist in its efforts. Interested parties can join the discussion list by sending an email. ®