Deep neural networks... IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI
Boffins point to benefits of putting rad-hardened ASICs in orbit
Boffins from the Delft University of Technology (TU Delft) and European Space Agency (ESA) have penned a paper detailing the design of a processor they hope could run deep neural networks in space – building on the free and open-source RISC-V architecture and its vector extensions.
"One of the main issues in terms of hardware faced by the space industry is that it is not possible to reuse in a straightforward way the hardware platforms employed in terrestrial applications," the researchers explained, "given the specific constraints of satellite data systems especially in terms of robustness to ionising radiation."
By way of example the team cited a 2019 paper [PDF] in which an off-the-shelf AMD graphics processor of the type commonly used to accelerate machine learning workloads was placed in the path of a proton beam to simulate radiation exposure in space – and proceeded to fail every 43 seconds, give or take.
Couple that with high-performance processors being typically energy-hungry too and the dream of running deep neural networks in space seems to be just that – a dream.
Which is a shame, because there would be benefits galore: "Sometimes onboard data processing provides an advantage over on-ground data processing in terms of satellite performance," the researchers claimed.
"For instance, data compression is already deployed in many missions because it mitigates the bottleneck of the downlink. The efficiency of the downlink can be increased even further, removing useless data instead of sending it to the ground. For instance, in the Landsat datasets the average cloud cover in an archived scene is 34 per cent, with 38 per cent of the scenes containing less than 10 per cent cloud cover.
"Therefore, selecting only images with less than 10 per cent of cloud cover results in an average of 2.63× data reduction. Combining data removal with a 2:1 compression, the amount of useful data sent increases by 5.26× compared with a system without on-board data processing."
Getting there will need new processors which offer the performance required at a fraction of the power draw of a typical GPU – while also being resistant to the hardships of space. Which is where, the team claimed, RISC-V could come in.
"Performances of space processors can be substantially improved with data-level parallelism (DLP) to achieve performance of the same order of magnitude of high-performance terrestrial processors for DNNs [Deep Neural Networks]," the team posited in the paper.
"To do this, we develop in more detail the study of the RISC-V processors needed to enable on-board decision making (OBDM), focusing on the preliminary design of a RISC-V vector processor specifically for space applications.
"This preliminary design is intended to serve as a baseline for future works, during the Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of a RISC-V vector processor for space applications based on the NOEL-V platform (developed by Cobham Gaisler)."
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The paper isn't Cobham Gaisler's first shot at putting a free and open-source instruction set architecture in space. In 1997 the ESA began using a 32-bit SPARC-V8 core dubbed LEON, developed at the European Space Research and Technology Centre (ESTEC), with the underlying VHDL code being released under a reciprocal licence by Jiri Gaisler – the "Gaisler" in "Cobham Gaisler" – in 1999.
Today, Cobham Gaisler offers a range of radiation-hardened, space-ready parts based on subsequent generations of the SPARC-based LEON core, and branched out into RISC-V with the release of the equally open NOEL-V core in December 2019.
RISC-V alone, however, doesn't offer the performance required for DDN operation in space. For that, vector extensions are required. Thankfully, RISC-V has exactly that, in the form of the RISC-V Vector Extension (RVVE).
"Although the RVVE is still in the process of being standardised," the researchers noted, "it plays such a crucial role in state-of-the-art applications that already several developments implementing the RVVE are described in literature."
Actually building a space-ready implementation would mean a step-change in the technology which reaches orbit, though. "The relatively large size and the focus on high performance of vector processors requires the identification of a radiation-tolerant ASIC [Application Specific Integrated Circuit] technology with a technology node around 28nm," the team said, "whereas state-of-the-art processors in space systems are typically still based on RHBD [Radiation Hardened By Design] 65nm technologies."
"The open and innovative nature of RISC-V makes it an excellent candidate for scientific applications," FOSSi Foundation and RISC-V director Stefan Wallentowitz told The Register. "Application in space is driven by different constraints to other applications and the availability of shared, open-source implementations of RISC-V will benefit such work."
The researchers, and Cobham Gaisler, were silent on when we might see the first RISC-V parts in orbit. The paper is available under open-access terms in the Journal of Aerospace Information Systems. ®