Chinese chip designers hope to topple Arm's Cortex-A76 with XiangShan RISC-V design

Permissively licensed, the processor's second iteration targets 2GHz at 14nm


The Institute of Computing Technology at the Chinese Academy of Sciences (ICT CAS) has showcased progress on a fully open-source processor, designed around the RISC-V architecture, which it hopes will offer competition for Arm parts at the performance end of the market.

Developed from the opening of a GitHub repository to booting Debian Linux in a matter of months, with work currently progressing on a higher-performance second iteration, XiangShan, or "Fragrant Hills", comes with bold promises as spotted by our friends at Heise. Once optimised, its creators claim, it will go toe-to-toe with Arm's top-end Cortex-A76 processor cores – and it will do so while being available under an open-source licence.

Designed with performance in mind, the first-generation XiangShan processor is an out-of-order design with an 11-stage pipeline depth, six issue width, and four memory access components, built for speed. Taped out for production at TSMC on a 28nm process node this month, the part reaches speeds of up to 1.3GHz with a benchmarked performance claimed at seven SPEC CPU 2006 points per gigahertz.

Arm-killing performance still a pipe(line)-dream

In other words, it's not quite living up to its Arm-killing hopes just yet. "The performance-to-power ratio of the [Arm Cortex-]A73 is very good, reaching a performance higher than that of the XiangShan processor under the width of the second launch [issue]," developer Yinan Xu explained, in translation, in the project's documentation. "The XiangShan is currently six [issues], so the efficiency of XiangShan is not as good as that of the [Cortex-]A73.

"Although our long-term goal in the future is to be in line with [Cortex-]A76, it is still in progress. We need down-to-earth iterative optimisation. The purpose of agile development is not to overtake a corner. The experience accumulated by Intel and Arm over the years, we also need to accumulate slowly."

Progress is definitely being made: the second-generation XiangShan processor, which the team is hoping to tape out by the end of the year, is expected to hit 2GHz on a 14nm process node and boasts a higher 10 points per gigahertz result on the SPEC CPU 2006 benchmark – though the team has not explained why it hasn't tested on the current SPEC CPU 2017 benchmark, which replaced SPEC CPU 2006 in June that year.

Free-as-in-speech a key feature

The key differentiator between XiangShan and Arm isn't performance, however, but in the licensing. The processor's design, written in the Chisel hardware description language (HDL) for its claimed efficiency improvements over rival HDL Verilog, is published under the Mulan Permissive Software Licence 2 (MulanPSL2) – a local equivalent to the Apache 2.0 licence.

As a result, it's possible to take XiangShan and mess with it to your heart's content – anything from experimenting with your own modifications and extensions to producing and selling physical chips. Thus far the team hasn't confirmed plans for its own commercialisation efforts but is in partnership with the Beijing Microcore Corporation, which has been named as "the first company to jointly develop with XiangShan."

While Bao Yungang, executive director of the Research Centre of Advanced Computer Systems at ICT CAS and colleagues may be targeting Arm's top-end parts on the performance side, they're not above borrowing a trick from Intel. Each generation of XiangShan microarchitecture is named after a lake, just as Intel names each generation of its own processors' microarchitecture.

The first microarchitecture is dubbed Yanqi Lake (Yanqihu), where some of the students working on the project spent a year; the second is Nanhu Lake (Nanhu), in honour of the 100th year of the Chinese Communist Party (CCP), which was reportedly founded aboard a boat on the lake.

Let's all meet up in the year 2051

"We have a hope that XiangShan can survive for 30 years," Bao claimed, in translation, in a recent presentation on the project. "We have an agreement to get together again in 30 years, and then see what XiangShan will become. However, to realise this desire, there are still many problems and challenges that need to be resolved."

Key among those challenges: scaling the development team up considerably. "The agile design process and platform [we] previously built supports a development team of more than 20 people, which is far from enough," Bao noted. "What we need to consider now is how to build a set of open source, open, and standardised open processes that can support the development of an open source community of 2,000 people."

The XiangShan source code, released under the permissive MulanPSL2 licence, is on GitHub; Bao's presentation on the topic has been published to Zhihu.com.

"The XiangShan project excellently demonstrates the power of an open source instruction set," RISC-V and FOSSi Foundation director Stefan Wallentowitz told The Register.

"RISC-V is an excellent candidate to start university and general R&D projects on computer architecture. Running such a project with many students as an open source project up to the point where it gets commercially interesting is an amazing validation of the power of free and open source silicon." ®

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