A quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their suitability for highly parallel workloads in science and beyond.
Born at the University of California at Berkeley in 2010, following an earlier research project from the 1980s dubbed Berkeley RISC, which would eventually become the SPARC architecture, RISC-V is both free and open source. As a result, anyone can build chips implementing the RISC-V architecture and can modify and expand it at will, adding new features or tweaking existing ones as required.
A paper presented at the Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), though, concentrates wholly on off-the-shelf RISC-V chips – introducing support for the Open Computing Language (OpenCL) heterogeneous programming framework commonly used to spread scientific workloads across CPUs, GPUs, and other accelerators.
"To the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community," the researchers explained in the abstract to their paper.
"Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research."
- As Europe hopes to double its share of global chip production, Intel comes along with $20bn, plans for fabs
- Nvidia launches Cambridge-1, UK's most powerful supercomputer, in Arm's neighbourhood
- Chinese chip designers hope to topple Arm's Cortex-A76 with XiangShan RISC-V design
- Arm chief hits out at 'ill-informed speculation' over proposed Nvidia buyout
The OpenCL implementation which resulted from the team's research required no changes to the processor designs themselves, and is compatible with a range of parts – from high-performance multi-core processors to low-profile embedded implementations. Including the latter proved a challenge: "[These] often do not support atomic instructions or multi-threading," the team found.
The team's work builds on the Performance OpenCL (POCL) project, an open-source OpenCL implementation which previously targeted a range of architectures including x86, Arm, MIPS, and general-purpose GPU (GPGPU) parts. POCL was first modified to bring support for Linux-capable higher-performance RISC-V chips, like that found powering SiFive's HiFive Unmatched, before moving to the embedded chips.
"Expanding the RISC-V ecosystem to include parallel applications via OpenCL opens the door to the large segment of scientific computing," the team concluded. "Furthermore, it provides hardware designers new workloads for exploring new microarchitecture designs and optimisations.
"Our extension [of POCL] particularly targets today's large segment of commodity RISC-V cores without SIMD vector extensions and also expands to low-profile embedded processors with minimal capabilities."
The work has been carried out alongside other efforts to boost RISC-V's presence in scientific computing, including several being pushed forward under the aegis of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC).