Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors
Startup co-founded by former Applied Micro X-Gene execs emerges from stealth
A Silicon Valley startup is stepping out of stealth mode today, publicly vowing to supply high-performance data-center-class RISC-V processors.
Ventana Micro Systems said since its founding in 2018 it has secured $53m in funding in series A and B rounds, the latter of which totaled $38m and was led by Marvell founders Sehat Sutardja and Weili Dai.
It is hoped the first samples of its 64-bit RISC-V processors will be shared with customers in the second half of next year, and ship in volume in the first half of 2023. It's worth remembering that big biz rarely significantly commits to using someone's silicon until it reaches second generation; the first generation is mostly for evaluation of the platform, which is where Ventana is at right now.
The processors, CEO and cofounder Balaji Baktha explained to us, will use a chiplet approach, as seen with AMD and lately Intel. That is to say, each chip will contain a number of discrete dies – some with CPU cores, some with custom acceleration, and others with IO and memory interfaces – interconnected within a single package.
The idea being that the compute and IO dies will be designed by Ventana, and the custom acceleration dies will be specified by the customer for a given processor, and the whole thing packaged by Ventana, using its foundry partners, for its individual clients. Up to half-a-dozen chiplets can be placed in a processor package.
At some point in future, a customer might take over the manufacturing, and assemble the dies themselves. For now, Ventana said it will oversee the production of the processors from design to verification to tape-out to fabrication and packaging by foundries to shipping for its clients. Some chiplets, notably the CPU dies, will use TSMC's 5nm node, we're told; the other dies can use the most appropriate node as necessary.
- Intel to put SiFive's latest CPU cores into 7nm dev system to woo customers to RISC-V
- RISC-V boffins lay out a plan for bringing the architecture to high-performance computing
- Android 10 ported to homegrown multi-core RISC-V system-on-chip by Alibaba biz, source code released
- Beagleboard peeps tease dual-core 64-bit RISC-V computer with GPU, AI acceleration, more for under 100 quid
These chips are expected to be, initially at least, used for things like control and data plane processors, and system-on-chips for security and storage appliances, for hyperscalers and similar businesses that build out a lot of their own servers and data centers and want to include specific functionality at the silicon level.
These customers were drawn to RISC-V because, for one thing, it allows them to extend the open, royalty-free instruction set architecture with their own custom instructions that accelerate particular tasks, according to Baktha.
These custom instructions appear to low-level programmers as RISC-V ISA extensions. Say you want your Ventana processor to accelerate data decompression. On one of the custom chiplet dies, you specify the digital logic to perform this task in hardware. When application or firmware code wishes to perform some decompression, it uses custom instructions also defined by the customer. The CPU core running that code sees those instructions and communicates with the custom die to complete the operations fast, and returns the results to the calling code. As far as the program is concerned, it was handled in no time by some CPU instructions when in fact the workload was handled by a connected die.
Some tasks are best handled by memory-mapped engines as seen in some other system-on-chips, though some will arguably benefit from being treated as if they were instructions.
All the dies are joined together using an interconnect designed by Ventana that is said to be cache coherent, has an access latency of 8ns, and can shift up to 16Gbps per lane. The startup believes this will be suitable for coherently connecting CPU cores, acceleration dies, on-chip storage, and interfaces that talk to off-chip RAM, PCIe devices, and other IO.
As a customer, you just have to make sure your custom die design obeys the interconnect's specification – said to follow the Open Compute Project's Open Domain-Specific Architecture (ODSA) physical interface standard – and it can be dropped right in. This is pitched as easier and cheaper than, say, licensing CPU cores from Arm and designing them into a system on chip with custom acceleration.
It also means that those instructions and connected functionality remain exclusive to the customers' chips for their own private use. In the past, if you asked Arm to extend its ISA, you might find that if Arm agreed, those instructions and features would end up being available to all licensees, which the big players weren't happy about. That said, Arm does now allow customers to add extra instructions to its Armv8-M microcontroller-grade cores.
Ventana's compute dies each feature 16 RISC-V cores. Baktha said these out-of-order, four-wide superscalar cores should outperform RV64 rivals and at least match Arm's Neoverse data-center-class CPUs.
Who's behind it?
Flicking through the list of Ventana staff on LinkedIn, we can see engineers and product managers who have spent years at Arm, Applied Micro, Ampere, AMD, Samsung, Intel, Xilinx, and other big names in the semiconductor world. They have plenty of experience in designing, verifying, and taping out 64-bit Arm and x86 CPU cores.
Ventana may look like a comeback by the team behind Applied Micro's X-Gene Arm server processors – the chip family from the early 2010s that failed to set the world on fire, and ended up the hands of private-equity biz the Carlyle Group, which today funds the more recent Arm server processor upstart Ampere. Baktha as well as Ventana cofounder and chief architect Greg Favor were, for instance, heavily involved in the development of the X-Gene series at Applied Micro.
But to us it looks more like Ventana is a collection of people from all parts of semiconductor world, not just Applied Micro, who having seen how the dominant processor designers – Intel, Arm, and AMD, mainly – have approached the enterprise world now want to do something different and better. In a way, with the nature of RISC-V, they want to be their own Arm.
Baktha said Applied Micro's data-center processor attempts stumbled because years old the Arm world didn't quite have the necessary server-friendly software ecosystem nor did Applied Micro have access to leading-edge fabrication process nodes. This time around, he said, Ventana can book capacity with TSMC and its state-of-the-art nodes, and the RISC-V ecosystem is shaping up, so his startup has a better chance of succeeding.
"We want Arm to succeed," he told us, quickly adding: "But there's plenty of room for everyone." ®