New release of SweRVolf RISC-V SoC project aims for lower barrier to entry

FOSSi Foundation's Olof Kindgren on the origins, future, and success of the RISC-V ISA

The SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising lower barriers to entry for those looking to experiment.

"Western Digital released the first of the SweRV cores, EH1, in 2018," Olof Kindgren, senior digital design engineer at Qamcom and director at the Free and Open Source Silicon (FOSSi) Foundation, told The Register.

"While it was an amazing core, and the fastest 32-bit RISC-V core at least at that time, they were new to the world of open-source silicon and asked me what they should do to make it easier for others to pick it up.

"One of my suggestions was to make an FPGA-based reference SoC so that software developers could quickly get started writing software to evaluate the core and hardware developers could use it to prototype SweRV-based chips. This was agreed upon and Qamcom got the job to create it under my lead.

"Out of the hundreds of available open source RISC-V cores, the SweRV cores stand out technically by providing some features that are clearly designed by people who have a ton of experience in building embedded hardware."

Kindgren was no stranger to the concept of free and open-source silicon, designs you can use without the usual demand for hefty royalty payments or non-disclosure agreements. "I had cut my teeth on OpenRISC – basically a precursor to RISC-V that was created in 1999 and planted the seed for the FOSSi ecosystem but never managed to achieve the same recognition – and spent a lot of time to both improve it technically and spread the gospel," Kindgren told us.

"As of now, there is no question that RISC-V is the answer. We have reached the point where the industry sees the benefit of rallying around an open ISA, which is a standard just like Ethernet, Python or JPEG, so that they can raise the abstraction and focus on their actual products instead of signing NDAs and fumbling with encrypted netlists. RISC-V lets companies focus on their core business, not their cores."

The SweRV core – or, in its latest release, cores – used in the SweRVolf project come courtesy of storage giant Western Digital. Developed in-house and based on a 32-bit implementation of the RISC-V instruction set, the technology was released by the company under the permissive Apache 2.0 licence – allowing absolutely anyone to use, distribute, or even modify the design to their heart's content.

"They are also very well documented, written in traditional SystemVerilog and are backed by a big consortium – CHIPS Alliance," Kindgren added, "which are all important points for the more conservative parts of the industry."

That highly permissive licensing approach extends to the SweRVolf project, too. "SweRVolf is also licensed under Apache 2.0," Kindgren told us, the same permissive licence as the SweRV cores themselves. "This was a requirement from Western Digital, but is also one of the licences – together with SolderPad and CERN OHLv2 – that we do recommend at the FOSSi Foundation."

SweRVolf, though, is more than just a processor core: it's a fully functional system-on-chip, featuring two interconnect systems – AXI and Wishbone – which connect the SweRV core to a boot ROM, system controller, and serial UART, along with external memory.

While not as feature-rich as most modern commercial SoCs, there's enough in there to boot and run a program – as proven by SweRVolf Nexys, a variant designed to run atop Digilent's Nexys A7 FPGA development board.

In its latest release, SweRVolf 0.7.4, a range of improvements were announced. The biggest was support for the more compact SweRV EL2 core unveiled in December 2019 as an alternative to the SweRV EH1 it was originally designed around. "This in turn has made it possible to use smaller and cheaper FPGA boards in addition to the Nexys A7," Kindgren explained.

"The newly supported [Digilent] Basys 3 board is popular within universities, which is a place where we will soon see SweRVolf in its RVfpga incarnation. I am also currently working on a very cool new feature that will even allow for users who don't have access to any hardware to use a virtual development board. I hope to share more about this later on."

Another improvement in the project's board support package (BSP) allows for Zephyr, the popular real-time operating system (RTOS), to automatically detect the SweRVolf's clock frequency at runtime – meaning a single binary can be used with SweRVolf implementations running at different speeds without recompilation.

A new demo application has also been added to take advantage of this compatibility feature, printing out the CPU type and detected clock speed.

While Kindgren is convinced that RISC-V is the path forward – "it was actually just less than three years ago when I started implementing SERV, the world's smallest RISC-V CPU, that I read the ISA specifications for the first time," he told us, "and really discovered what a work of art it was" – there's some nostalgia for the days of OpenRISC.

"Almost all of the selling points they brought up for RISC-V were also things that we already planned to address in an updated version of OpenRISC intended to be called OpenRISC 2000," Kindgren explained.

"I met David Patterson [vice-chair of the RISC-V Foundation, coiner of the term 'Reduced Instruction Set Computer,' and co-creator of the Berkeley RISC project] a few years later at a RISC-V workshop and introduced myself as coming from the OpenRISC project and how it had led me into RISC-V. He smiled and said, 'Oh, you guys were just too early,' which felt like a great validation of our work."

The latest version of SweRVolf, with full source code, is available on the CHIPS Alliance GitHub repository. ®

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