HPC

First RISC-V computer chip lands at the European Processor Initiative

EPAC accelerator runs its first 'Hello, World!' in-silico


The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware.

EPI, launched back in 2018, aims to increase the independence of Europe's supercomputing industry from foreign technology companies. At its heart is the adoption of the free and open-source RISC-V instruction set architecture for the development and production of high-performance chips within Europe's borders.

The project's latest milestone is the delivery of 143 samples of EPAC chips, accelerators designed for high-performance computing applications and built around the free and open-source RISC-V instruction set architecture. Designed to prove the processor's design, the 22nm test chips – fabbed at GlobalFoundries, the not-terribly-European semiconductor manufacturer spun out of AMD back in 2009 – have passed initial testing, running a bare-metal "hello, world" program as proof of life.

It's a rapid turnaround. The EPAC design was proven on FPGA in March and the project announced silicon tape-out for the test chips in June – hitting a 26.97mm2 area with 14 million placeable instances, equivalent to 93 million gates, including 991 memory instances.

While the FPGA variant, which implemented a subset of the functions of the full EPAC design, was shown booting a Linux operating system, the physical test chips have so far only been tested with basic bare-metal workloads – leaving plenty of work to be done.

The EPI has been funded as part of the European Union's European High-Performance Computing Joint Undertaking, EuroHPC – of which the UK is not a member. Its membership roster is a who's who of European technology firms and academic institutions spanning 10 countries and including France's Atos, the Italian arm of STMicroelectronics, Germany's Infineon and Fraunhofer-Gesellschaft (FhG), the BMW Group, the Barcelona Supercomputing Centre (BSC), ETH Zürich, Instituto Superior Técnico, the University of Zagreb, and the Foundation for Research and Technology (FORTH) in Greece.

The EPAC 1.0 chip is an undeniable team effort: it includes "micro-tile" vector processing cores designed by SemiDynamics, a dedicated vector processing unit from the Barcelona Supercomputing Centre and the University of Zagreb, a "home node" designed by Chalmers, L2 cache from FORTH, a Stencil and Tensor Accelerator (STX) from Fraunhofer, ITWM, and ETH Zürich, and a variable-precision processor – designed to accelerate deep learning workloads – created by CEA LIST, all tied together with a network-on-chip and high-speed serial system created by EXTOLL.

It's also only one of three technology streams under investigation at the EPI. The second is a general-purpose processor (GPP) which will adopt the accelerator as a node alongside central processing unit cores and an embedded FPGA (eFPGA). The third is the automotive stream, in which the technologies developed in the GPP stream will be taken out of the data centre and put into vehicles for acceleration of autonomous driving system (ADS) workloads.

The European Union is far from alone in looking to lower its reliance on foreign technologies. Earlier this year Russia revealed a national digitalisation programme which centred around RISC-V parts, on top of the nation's existing homebrew Elbrus chips; China, meanwhile, is hard at work on a high-performance RISC-V chip family called XiangShan, and plans to deploy 2,000 RISC-V laptops by the end of next year. India's "Atmanirbhar Bharat" programme for self-sufficiency extends to processors, too, with RISC-V designs ranging from scalable parts to EPI-like supercomputer chips.

The EPI project has confirmed it is working to validate the other IP blocks on the chip, which targets a 1GHz operating frequency in its current FCBGA-packaged test-chip incarnation, as well as furthering the EPAC design's development and optimisation. It did not respond to a query as to the state of its roadmap in time for publication.

"Open-source silicon is an excellent enabler for ventures like the EPI," Stefan Wallentowitz, director at RISC-V International and the FOSSi Foundation, told The Register. "Leveraging open-source components to build modern and future high performance computing platforms demonstrates the potential of open source silicon, and helps in building the community around it. We hope to see this effort evolve into more cooperation and openness."

Assuming the project remains on-track, the first EPI general-purpose processor, which mixes RISC-V and Arm cores, will be unveiled next year. ®

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