PCIe 6.0 spec just months away from completion, doubles max data transfer rate
Or will do in practical terms when devices start appearing, anyway
A key standard set to double data transfer speeds between the main components of computers will be finalized in a matter of months.
The final specification for PCI-Express 6.0 is targeted for the end of this year or early 2022, Al Yanes, president and chairperson of the standards organization PCI-Special Interest Group, told The Register this week.
"The rule of thumb is that we typically see products utilizing the latest PCIe architecture 12 to 18 months after final specification release," Yanes added.
You know the drill: PCIe typically links up microprocessors, GPUs, IO devices, and data storage in systems ranging from home PCs to cloud servers to some embedded devices. PCI-SIG is in the final stages of approving the specification, and released what may be its last revision, version 0.9, today.
The 6.0 spec supports up to 64 gigatransfers per second, which in practical terms means up to 128 GB/s per direction in a x16 configuration, which is double that of PCIe 5.0. By comparison, PCI-Express 1.0, which was released in 2003, had a transfer rate of 2.5 GT/s, which translates to 4GB/s per direction with x16. PCI-Express 6.0 will be backwards compatible with previous generations, we're told. Upgrades to the PCI-Express standards have been in increments of two years since PCIe 4.0, which was ratified in 2017.
The faster transfer rates are needed due to the rise in data-hungry applications that include artificial intelligence, Yanes said.
"PCIe 6.0 technology bandwidth capabilities are more suited for high end applications at this time... accelerators, machine learning and HPC applications that need high IO bandwidth," he told us.
- Buy, buy this American PCIe, drove my PC on the Wi-Fi so the Wi-Fi would fly
- Dual carriageway to autobahn: Intel revs up Optane caching memory by doubling PCIe lanes
- Compute Express Link glue that binds processors and accelerators hits spec version 2.0... so, uh, rejoice?
- It sounds like a new train line, but no: Compute Express Link is PCIe 5.0 server CPU-accelerator glue from Intel and pals
The protocol has gained a low-latency data error correction mechanism called forward error correction (FEC), in addition to CRC, to make the increased bandwidth viable. It also, interestingly enough, uses PAM-4 [PDF] encoding, which is seen in fast Ethernet and GDDR6X. There are other tricks up its sleeve – a technical overview is here [PDF].
It will be a while until PCs get PCIe 6.0 interfaces. If not because it's going to take extra care to lay out motherboards that can handle the high-speed signalling, then because the chipsets just won't be ready.
An Intel spokesperson declined to comment on when it would add PCIe 6.0 support to its components, though said it was supporting PCIe 5.0 in the upcoming processors code-named Alder Lake; its Sapphire Rapids and Ponte Vecchio will support PCIe 5.0, too. Otherwise the latest Intel Xeon and 11th-gen Core parts support PCIe 4.0.
An Nvidia spokesperson declined to comment on when it would bring in PCIe 6.0 support. The company's chips, like the BlueField-3 DPU for data centers, can handle PCIe 5.0. AMD did not respond to a request for comment. The biz's most recent desktop and data-center chips support PCIe 4.0, we note.
The evolving automotive sector is hot on semiconductors, and PCI-SIG is looking to cash in.
"We have seen tremendous interest in automobile solutions and we have formed a new PCIe technical workgroup to focus on how to increase the adoption of PCIe technology in automobile industry due to the increased demand for bandwidth in that ecosystem," Yanes said. ®