This article is more than 1 year old
'We will not rest until the periodic table is exhausted' says Intel CEO on quest to keep Moore's Law alive
From developers and Mount Evans ASICs to zettascale-by-2027 promises – what's Chipzilla got planned for us?
Analysis Intel won't give up on Moore's Law, even though just about everyone has declared it dead or on its way out.
"Moore's law is alive and well," said CEO Pat Gelsinger during a keynote at the Intel Innovation event, which was webcast on Wednesday.
He showed a chart tracking the semiconductor giant progressing along a trend line to 1 trillion transistors per device by 2030. "Today we are predicting that we will maintain or even go faster than Moore's law for the next decade," Gelsinger said.
If there was one point Gelsinger, who became CEO early this year, tried to hammer home, it was of Intel returning to its heritage of focusing on developers and hardware engineering.
It seems Intel's trying to discover its roots after seeing its industry leadership role slip following many missteps. Intel is losing ground to Apple, Arm, and AMD, and Taiwan Semiconductor Manufacturing Co. and Samsung caught up, if not jumped ahead, on manufacturing.
For more than a decade Intel has tried to broaden its mass appeal through efforts like dazzling displays of drones and robots, and an attempt to launch a TV streaming service. After hiring will.i.am as a creative director and getting involved in X Games, the manufacturing titan abandoned its annual developer event, IDF, after it turned into a awkward carnival for cool creations with its tech.
Intel used Moore's Law for decades as a foundation to reduce the size and cost of chips. The corollary is based on an observation by Intel co-founder Gordon Moore in 1965 that the number of transistors on silicon would double every two years to improve chip functionality and performance. But scientists for years have declared Moore's Law as being dead or on its way out.
AI chip maker Cerebras says it has put 2.6 trillion transistors in a chip the size of a wafer that would not fit in your regular computer. Apple recently put 57 billion transistors in its Arm-compatible M1 Max chip, which was announced this month and is in the MacBook Pro.
The road ahead
The path to maintaining Moore's Law is through new manufacturing and chip packaging technologies the company will implement, said Gelsinger.
"Gordon understood the importance of packaging and said as much in his original paper," Gelsinger said referring to this document [PDF].
It should be feasible for Intel to stick with Moore's Law with advanced packaging of chips, and there's a lot of work to be done on shrinking ahead with gates all around devices, backside power delivery, and CMOS, said David Kanter, executive director at MLCommons, a standards-setting organization for AI chips.
"There is a long list of other technologies we can exploit to improve density - in many respects the limitations aren’t technical, but rather are economic. 2D semiconducting materials are another future step here," Kanter said, adding: "The art of maintaining Moore’s Law is about exploring those options and then finding the right ones to deploy into production at scale."
Pat Gelsinger pictured next to a graphic of a next-gen FinFET – a gate-all-around device called a RibbonFET. Source: Intel webcast
Intel is focused on developing RibbonFET devices, next-generation FinFETs that could well deliver better performance and power efficiency over today's transistors. With RibbonFET, the transistor's channels are lifted up into the gate fin so that the gate material surrounds the channels, which increases the contact area. That helps chip designers reduce current leakage, and achieve faster transistor switching speeds and thus better performance. RibbonFETs are due to be used on Intel's upcoming process nodes, such as the Intel 20A (aka Intel 5nm) from 2024.
The ribbon approach will allow Intel to design structures "where we might have two, three or four of these ribbons giving us different sizes of transistors," Gelsinger said, allowing engineers to select the density and performance as required.
"Performance now comes from more than just transistor dimensions. Yes, we are printing them even smaller, but it also comes from different types of transistors optimized for different types of needs, and putting together architectures that are tailored for software workload needs." .
Another key technology is extreme ultraviolet lithography, which helps semiconductor companies print chips in much finer detail and at lower costs. Rivals Samsung and TSMC are using EUV.
Intel is also researching new materials to include in chips. "We will not rest until the periodic table is exhausted," Gelsinger said.
After replacing Robert Swan as CEO, Gelsinger put manufacturing at the top of his priority list. The company promised to operate as a contract manufacturer – it's said that before but this time, it really means it, apparently – that will also make Arm and RISC-V chips as well as x86 parts.
Google Cloud collaboration
Speaking of Arm: in August, Intel said it had created Mount Evans, an IPU ASIC – that's infrastructure processing unit – that included 16 Arm Neoverse N1 CPU cores plus IO interfaces, caches, and a packet-processing pipeline. The idea being that data center infrastructure work, such as network management, can be offloaded to the IPU to handle, freeing up the host Xeon server processors for application code.
It turns out Intel designed this ASIC with the help of Google Cloud, where the component is set to be deployed. Other buyers will be able to get their hands on the family of chips, too. Intel will allow the specialized silicon to be controlled using an Infrastructure Programmer Development kit.
IPUs, or DPUs, or Smart NICs, or whatever you want to call them are hot right now, with Marvell, Nvidia, and others getting into the game.
- Intel claims first Alder Lake chip is the fastest desktop gaming silicon in the world
- Raising the price of in-demand processors really helps the bottom line, says AMD
- Intel hopes to burn newly open-sourced AI debug tech into chips
- Apple kicked an M1-shaped hole in Intel's quarter
Intel is investing $20bn on building two advanced chip factories in Arizona, and hopes to cash in on chip shortages affecting industries that include consumers electronics and automotive: where there's demand outstripping supply, there's a profit to be made.
Intel has had its Moore's Law missteps. In 2014, the chip maker was below the Moore's Law trend line on cost reduction on its 14nm process node compared to previous manufacturing processes. That set the ball rolling on the company failing to meet its typical two-year manufacturing cadence to advance to the 10nm process, which led to chip cancellations and restructuring of the product roadmap.
The company on Wednesday also announced developer tools including PCs designed for data scientists; the OneAPI toolkit to simplify programming in heterogenous chip architectures; and a consolidated Intel DevCloud development environment to test and run code on the company's latest CPUs, GPUs, FPGAs and other chips.
The tech giant also announced the 12th Generation Intel core chips code-named Alder Lake, which is based on its hybrid architecture that mixes high-performance and power-efficient cores.
He zetta what?
In a Q&A session after his keynote, Gelsinger revealed that achieving zettascale computing using Intel technology "in 2027 is a huge internal initiative."
Stepping back down to exascale, Gelsinger also said the much-delayed Intel-powered Aurora supercomputer, destined for US government lab work, will achieve a peak performance exceeding 2 exa-FLOPS.
Given that Aurora, which was supposed to run in the order of 1 exa-FLOPS, isn't due until at least 2022 after years of setbacks, you should take the CEO's hopes for the machine, let alone zettascale targets for 2027, with a decent pinch of salt. ®