China's road to homegrown chip glory looks to be going for a RISC-V future

The RISC-V Summit is over - here's what you need to know

China's been scammed for billions by rogues in its chase to become a chip powerhouse, though ironically, a free, open-source CPU architecture is emerging as its best bet to create a powerful homegrown chip.

China was a winner at this week's RISC-V Summit, with many organizations introducing CPUs based on RISC-V, an open-source chip architecture sometimes called the Linux of chips. The government-backed Chinese Academy of Sciences, which is on the US Entity List, and StarFive Technology released new RISC-V chip designs for PCs and servers.

The profile of RISC-V is growing with backing from companies including Apple, Intel, Google and Nvidia. And RISC-V development is especially picking up in China, with Alibaba in October opening code of the XuanTie custom-built processors based on RISC-V instruction, and is porting Android 10 to RISC-V ISA.

The country has poured billions into making homegrown chips with the aim of being self-sufficient in the technology. Another goal is to cut the reliance on foreign countries, with chip technology being used as leverage by US in its trade war against China.

For example, the US is limiting chip technology exports to the Chinese Academy of Sciences, which has now turned to RISC-V for CPU development. The organization in 2010 developed the MIPS-based Loongson chip, and the latest chip release earlier this year mixes MIPS with RISC-V.

RISC-V is attractive to China because it is a borderless architecture, and it isn't controlled by a single company or government entity, Nathan Brookwood, chip analyst at Insight 64, told The Register. Other open-source efforts like OpenPower, which is led by IBM, are concentrated around vendors.

RISC-V provides a chance to break away from the monolithic structure driving the development, production and distribution of chips, and to create a level playing field for smaller chip makers, Brookwood said.

Move fast and break stuff

"We take advantage of the community. We break down corporate barriers, country barriers, cultural barriers, timezone barriers, and we all share that piece because we all know is that we are part of this community," Mark Himelstein, chief technology officer at RISC-V International, told The Register.

The newer Chinese chip designs introduced at RISC-V Summit aren't as advanced as the fastest x86 and Arm CPU cores, though the goal is to produce a competitive alternative with richer features, if not the latest and greatest eventually.

The Chinese Academy of Sciences announced the latest addition to the open-source XiangShan 64-bit chip family, dubbed Nanhu, which will tape out next year. This second-generation design operates at 2GHz, and is close to twice as fast as its first-generation predecessor, the Yanqihu, which was released six months ago and targets a 28nm process.

Nanhu is designed for a 14nm process, which means the chip could be made inside China at a fab run by SMIC, which operates at that node. While not as advanced as the cutting-edge 5nm and 4nm nodes run by Taiwan Semiconductor Manufacturing Co., Nanhu does close the manufacturing gap.

Just 30 people – 25 graduate students and five engineers – worked on the RISC-V-compatible Yanqihu, said Yungang Bao, a professor at Chinese Academy of Sciences' Institute of Computing Technology, during a presentation at the RISC-V Summit in San Francisco. Given the cooperative nature of RISC-V, some of Nanhu's features draw from open-source blueprints, such as SiFive's Block Inclusive Cache, the professor said.

"For us, we will not launch a startup to commercialize, but we hope there are some other companies to do that," Yungang said, adding: "We would like to see a company like Red Hat for RISC-V."

StarFive meanwhile introduced Dubhe, an out-of-order mainstream computing chip design that operates at 2GHz on Taiwan Semiconductor Manufacturing Co.'s 12nm process.

The microprocessor includes various RISC-V extensions, such as the bit manipulation one also implemented in XiangShan, plus an implementation of the newly ratified RISC-V hypervisor extension. That's the virtualization extension SiFive's top-end P650 RISC-V CPU core also supports.

There are challenges. If Nvidia doesn't acquire Arm, a merger that now looks highly unlikely, this failure could be a temporary roadblock in RISC-V's expansion, Brookwood said.

Arm is more like a Switzerland of the semiconductor world with its neutral stance. Companies were ready to ditch Arm if Nvidia took control, and that exodus may slow if the takeover doesn't happen, Brookwood said.

Meanwhile, some SiFive executives told us that, in their mind, it doesn't matter if Nvidia absorbs Arm or not: if it does, RISC-V looks more attractive, and if it doesn't, Arm will be left facing off against a growing number of RISC-V processor designers, they argued. ®

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