Intel sticks with FPGAs and ASICs for next-gen IPUs
Chip giant sticking with multi-architecture ASIC/FPGA approach through 2024
Intel Vision Intel's two-pronged ASIC/FPGA infrastructure processing unit (IPU) strategy was on full display at this week's Intel Vision event, where the chipmaker teased its upcoming 400Gbit/sec and 800Gbit/sec devices.
According to Patty Kummrow, GM of Intel's Ethernet division, the company is seeing strong demand for domain-specific processors – like IPUs – everywhere from hyperscale datacenters to the edge.
"IPUs are really fundamentally changing how the datacenter can be architected," she said during a press briefing.
Intel's IPUs – sometimes referred to as smartNICs or data processing units (DPUs) – offload and accelerate input/output-intensive workloads commonly associated with networking, storage, and security applications.
"IPUs give us some pretty incredible advantages. One of them is a separation of infrastructure and tenant workloads," Kummrow explained. "When we offload these infrastructure functions and free up the CPU cores to do the tenant workloads, we can also accelerate them. The IPU is purpose-built hardware for those functions."
A two-pronged approach
While Intel's updated roadmap offered little in terms of fine detail regarding its next-gen IPUs beyond higher throughputs, the chipmaker revealed it would at least stick with the multi-architecture ASIC/FPGA approach through 2024.
Intel's 400Gbps Mount Morgan and Hot Springs Canyon IPUs are slated for release in late 2023 and early 2024, while the chipmaker plans to bring 800Gbps IPUs to market in 2025 and 2026.
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Intel also offered a more concrete ship date for its upcoming Mount Evans and Oak Springs Canyon IPUs – if you count "later this year" as concrete. Chipzilla doesn't exactly have the best reputation for meeting deadlines with its upcoming Sapphire Rapids Xeon refresh and 7nm manufacturing process already behind schedule.
Introduced at last year's Intel Architecture Day, Mount Evans is the chipmaker's first ASIC-based IPU. The 200Gbit/sec smartNIC is designed for hyperscale datacenter environments where performance is the highest priority. The chip is already slated for deployment by Google and "other service providers," we're told.
The Agilex FPGA-based Oak Springs Canyon, meanwhile, sports the same 200Gbps of throughput as its ASIC-based sibling, but is targeted at communications service providers.
According to Kummrow, this multi-faceted approach balances customers' performance needs against their flexibility requirements.
For example, with Oak Springs Canyon, "customers that have changing workloads that they want to run on these devices can reprogram them at will," she said, adding that Intel's ASIC-based Mount Evans IPU may not be as flexible, but offers a better power/performance ratio.
"With an ASIC SoC, there's going to be more performance and power optimization because those functions are committed to hardware," she added.
Despite their disparate architectures, both the chipmaker's ASIC and FPGA-based IPUs are programmed via a common language: the infrastructure programmer development kit (IPDK).
IPDK is key to helping developers unlock the value of the hardware underneath, Kummrow said. ®
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