First details on TSMC's 2nm node: Chipmaker reveals nanosheet transistors

Plus: enhancements to 3nm tech due to go into production later this year

Taiwanese chipmaker TSMC has revealed details of its much anticipated 2nm production process node – set to arrive in 2025 – which will use a nanosheet transistor architecture, as well as enhancements to its 3nm technology.

The newer generations of silicon semiconductor chips are expected to bring about increases in speed and will be more energy efficient as process nodes shrink and the tech industry continues to fight to hang onto Moore's Law.

The company is due to go into production with the 3nm node in the second half of this year.

TSMC showcased its upcoming manufacturing process technology at the company's 2022 North America Technology Symposium, with the highlight being details of its next-generation 2nm node, known internally as N2.

TSMC's 2nm dies will be delivered to designers in volume in 2026 – meaning those chips could be available for phones, PCs, and servers that year.

N2 will see TSMC switch to a nanosheet transistor architecture rather than the fin field-effect transistor (FinFET) design that has been standard in the industry for some time in order to deliver improvements in performance and power efficiency.

The nanosheet architecture involves the electrical current flowing through several stacked layers of silicon that are completely surrounded by the transistor gate material. IBM claimed to have made the first 2nm chips using nanosheet technology last year.

TSMC said it expects to start producing chips using its N2 node in 2025, and that it will enable devices with a 10 percent to 15 percent speed improvement at the same power, or a 25 percent to 30 percent power reduction at the same speed.

The N2 node generation is planned to include a high-performance version as well as a mobile compute baseline version, plus various chiplet integration solutions, TSMC said.

TSMC's first customers for the N2 node could be Intel or Apple, according to earlier reports, which claimed that Intel plans to outsource the manufacturing of a graphics tile for its next-generation client processor – code named Lunar Lake – to TSMC.

Meanwhile, the N3 node generation is set to enter volume production later this year, and TSMC is introducing an enhanced version, N3E, using FinFlex technology that is intended to offer chip designers the flexibility of mixing different standard cells on the same die. This will allow them to create chip layouts using the most optimal configuration for each functional block to try to achieve the desired performance and power requirements.

The options comprise a 3-2 Fin configuration for the fastest clock frequencies and highest performance, a 2-2 option that provides a balance between performance, power efficiency, and density, and a 2-1 Fin configuration that TSMC claims offers the lowest power consumption, lowest leakage, and highest density.

Other developments include a new ultra-low power option, which TSMC said will build on the N12e technology it introduced in 2020. Known as N6e, this will be based on TSMC's 7nm process node and expected to have three times the logic density of N12e, but targets the same mix of logic, RF, analog, embedded memory, and power management chip applications.

Bringing all these chip manufacturing processes into production costs money, of course, and chipmakers around the world are expected to increase spending on equipment by 20 percent to an all-time high of $109 billion in 2022, with Taiwanese outfits such as TSMC leading the way.

TSMC announced in January that it expects to increase capital spending by nearly a third to as much as $44 billion in 2022 in order to build out production capacity. ®

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