RISC-V International emits more open CPU specs
First edicts of 2022 include firmware, hypervisor-level specifications
Embedded World RISC-V International has grown its pile of royalty-free, open specifications, with additional documents covering firmware, hypervisors, and more.
RISC-V – pronounced "risk five", and not to be confused with the other architecture of that name, RISC-5 – essentially sets out how a CPU core should work from a software point of view. Chip designers can implement these instruction set specifications in silicon, and there are a good number of big industry players backing it.
The latest specs lay out four features that compatible processors should adhere to. Two of them, E-Trace and Zmmul, will be useful for organizations building RISC-V hardware and software, and the other two could prove important in future, aiding the development of OSes to run on RISC-V computers.
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One of these is the UEFI boot protocol that specifies how system firmware obtains and handles information about the hardware before loading an OS kernel. Another defines a Supervisor Binary Interface (SBI) between the hardware and an operating system or hypervisor kernel, complete with a reference implementation by Western Digital called OpenSBI.
RISC-V International CTO Mark Himelstein said this was a "critical resource," offering "the ability to port supervisor-mode software across all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere."
As for the others, the E-Trace specification allows for efficient processor-branch tracing on RISC-V devices. If that's your sort of jam, there's a 100+ page PDF on GitHub.
The Zmmul extension specifies multiplication math support, with no division, primarily for small and simple embedded cores – there are already separate extensions for integer and floating-point math, including multiplication and division, for general-purpose application CPU cores.
(Historical RISC-y side note: the original Acorn ARM1 processor didn't have hardware for either multiplication or division, but it did have a barrel shifter.)
The RISC-V instruction set architecture is still in its very early days, and as some at The Reg have opined before, its future success remains far from certain. There isn't much general-purpose end-user RISC-V hardware out there that you can buy and try yourself, or fire up an emulator like Qemu.
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One of the few examples is the optional RISC-V processor module for the ClockworkPi DevTerm. One of the first reviews of the RISC-V version is on former TenFourFox browser maintainer Cameron Kaiser's blog TalosSpace, and while he likes the device a lot, the review is very negative about the performance of the machine's Allwinner single-core system-on-chip.
For now, RISC-V presents no real threat to anyone on the higher-end mainstream general-purpose CPU performance front. Apple has showed that investing a lot of time and money in making a large-scale highly integrated Arm SoC was thoroughly worth it, whether measured in raw performance, or performance per Watt, or price:performance. Now, the rest of the Arm industry has to catch up with Apple, while RISC-V still has to try to catch up with Arm.
Saying that, back in the day at least, the Arm world was a Silicon Wild West with every chip different, and it took a lot of industry effort and cooperation to, in some areas, standardize on things like firmware and the boot process. It's why a project like Armbian emerged. Kudos to RISC-V International for realizing that and tackling this at an early stage. ®
The RISC-V name comes from it being the fifth generation of the original Berkeley RISC design. The RISC-I chip had 78 registers, but its performance was disappointing (see the unusually discursive Wikipedia article before someone deletes it). Nonetheless, it inspired Sun's original SPARC processor.
RISC-II had a remarkable 138 registers. RISC-III was the SOAR CPU (Smalltalk On A RISC), and RISC-IV the processor for SPUR (Symbolic Processing Using RISCs), a very early parallel-processor workstation.