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SiFive RISC-V CPU cores to power NASA's next spaceflight computer
After more than two decades, the space agency's PowerPC love affair appears to be at an end
Chip designer SiFive said Tuesday its RISC-V-compatible CPU cores will power NASA’s just-announced High-Performance Spaceflight Computer (HPSC).
The computer system will form the backbone for future manned and unmanned missions, including those to the Moon and Mars. Its microprocessor will be developed under a three-year $50 million contract with SiFive and Microchip, the system-on-chip designer and home to the PIC microcontroller family.
The HPSC's processor replaces the aging PowerPC-based BAE RAD750, which was introduced more than two decades ago, and has flown in countless spacecraft, including the Curiosity and Perseverance rovers and the James Web Space Telescope.
“The last chip that NASA used lasted decades,” Jack Kang, senior veep of business development at SiFive, told The Register. “This chip is going to be used for the next multiple decades.”
SiFive claims the 12-core processor it's designing with Microchip will deliver a 100-fold improvement in performance over its predecessor while offering superior power efficiency thanks to its ability to turn off various sections of the chip when not in use. This performance is important, Kang said, to enabling a new generation of autonomous rovers, vision processing, spaceflight, guidance, and communications applications beyond Earth's atmosphere and orbit.
“A lot of these things are really well suited for vectors,” he said, referring to vector math.
Speaking of which, the HPSC processor will feature eight of SiFive’s AI/ML-optimized X280 vector-processing cores in addition to four general-purpose RISC-V CPU cores.
The X280 is a RISC-V CPU core with advanced vector math extensions. As its name suggests, it expands on the standard RISC-V instruction set architecture (ISA), meaning it can run application code as well instructions to speed up the processing of vectors by doing it in hardware.
SiFive claims these vector extensions enable the chip designer to achieve six-times higher performance than standard RISC-V vector instructions, while maintaining the platform’s low-power envelope.
However, beyond sheer performance, chips bound for the outer space must contend with harsh operating conditions.
“If you look at these chips that are going into space and these environments, there’s a lot they have to do,” Kang said. “Some of that comes from the architecture; some of it comes from the chip design itself; some of it comes from the process.”
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Architecturally, he says, SiFive’s design benefits from the company’s work developing chips for automotive applications. “Automotive has very similar type requirements when it comes to high reliability, fault tolerance, functional safety,” Kang said.
The RISC-V has garnered considerable attention and hundreds of millions of dollars in investment in recent years, thanks in part to its ISA's open, free, and light-weight nature. The base architecture, as a classic RISC design, features fewer than 50 instructions on which both official and third-party extensions can be added bring more instructions to a CPU core, to suit its operating requirements.
For instance, if you don't want floating-point math acceleration, you can stick to the integer base and extensions. But if you want an FPU, support for atomic instructions, and other features, you're free to implement those defined extensions in your CPU core.
NASA and Microchip’s decision to opt for a RISC-V design had to do with more than the novelty of an open and royalty free ISA. According to Kang, the RISC-V architecture is one of the more likely to have a large developer base 10, 15, or even 20 years from now, and thus would be a safe bet by NASA.
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“If you look at the current PowerPC chips — we’ve used them for decades — how many PowerPC programmers are there now,” he said.
While we now know the underlying CPU architecture behind NASA’s HPSC processor, we must wait to see how the design will ultimately be implemented, such as what radiation hardening will be used as well as any other specialized treatments required by space-faring semiconductors.
This is likely one of the reasons NASA tapped Microchip to develop the HPSC processor: Microchip advertises several radiation-hardened chips. Thus, SiFive provides the CPU IP while Microchip lays the cores out on a suitable space-survivable die with the necessary support circuitry – and bam, RISC-V in space.
“This cutting-edge spaceflight processor will have a tremendous impact on our future space missions and even technologies here on Earth,” said Niki Werkheiser, director of technology maturation within the Space Technology Mission Directive at NASA, in a statement.
“This effort will amplify existing spacecraft capabilities and enable new ones and could ultimately be used by virtually every future space mission, all benefiting from a more capable flight computing.” ®