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NIST and uni friends to design open source research chips, Google to bankroll the fabs

At 130nm, we'll take it

NIST has decided, with participating colleges, to design open source chips to help lower the barrier for those hoping to get into the world of semiconductors.

Announced on Tuesday, the US government's tech standards body said it will work with universities to develop chip blueprints that can be freely used or adapted by, for instance, academics and researchers at small businesses to produce their own specialist components.

Such a move may make it easier, and cheaper, for organizations and teams to design and test experimental chips ahead of any full-blown manufacturing.

These open source designs, according to NIST, will be made available "without restriction or licensing fees" for others to use.

Google – which has lately shown great interest in manufacturing chips for open source projects – will cover the cost of setting up production and will subsidize the first run of chips designed under the program.

Manufacturing will take place at SkyWater’s foundry in the Twin Cities suburbs in Minnesota using 200mm wafers. SkyWater and Google are known close partners.

Thus, this program seemingly seeks to lower the barrier to entry on two fronts: one, with open source blueprints being made available for others to build on, and two, with Google subsidizing the manufacture of a number of these chips.

According to NIST, the relatively high cost associated with producing experimental and short-run chips presents a non-trivial hurdle to university researchers and startups seeking to try out novel and interesting approaches in semiconductor design. They basically can't afford to get a batch of dies made, or it eats up most their budget, and makes the whole thing too risky or impractical for some to undertake.

By easing production of these chips, and making licensing affordable or restriction-free, NIST aims to dramatically reduce the cost of semiconductor research in the US. It also, handily, gives Google and SkyWater plenty more data on what works and what doesn't in the world of chip design and fabbing.

“By creating a new and affordable domestic supply of chips for research and development, this collaboration aims to unleash the innovative potential of researchers and startups across the nation,” said NIST Director Laurie Locascio, in a statement.

The open source nature of the program extends to the process node technology itself.

“NIST will be using the open source SKY130 technology node developed by Google and SkyWater,” explained NIST physicist Brian Hoskins, in an email to The Register.

Not quite cutting edge

While open, the process nodes available under this program is practically ancient compared to leading-edge nodes by Intel, TSMC, Samsung, or even GlobalFoundries, which range from 12nm to 3nm.

According to SkyWater's GitHub page, SKY130 is based on a mature 180nm to 130nm process node first developed by Cypress Semiconductor before it was spun out as SkyWater Technology.

These nodes, as we've explained before, can be useful for teams doing their first-ever tape-outs, mixed-signal chips, simple microcontrollers and ASICs with experimental physical features, and so on.

Once the program is up and running, NIST expects to design as many as 40 chips optimized for various applications. Many of these designs will be influenced by submissions from NIST’s university partners.

As such, these chips won't seem very traditional: they will instead allow scientists to try out things like putting specialist sensors on dies. “The majority of the test structures being built aren’t digital logic circuits. They are primitive test structures for testing manufacturing of nanoelectronic devices and biosensors,” Hoskins said.

With that said, some of the chips will feature at least one RISC-V CPU core, Hoskins added. Launch partners include the University of Michigan, University of Maryland, George Washington University, Brown University, and Carnegie Mellon University in the United States.

NIST plans to kick off its collaboration with Google during a virtual workshop running September 20 to 21, where the agency will discuss public participation in the program.

The collaboration comes just a week after the US Commerce Department sliced off $11 billion of the $52 billion in CHIPS Act funding for research and development. The funds will support the creation of two NIST subgroups, which share many of the same goals as the program announced today.

The first of these subgroups is the National Semiconductor Technology Center (NSTC), which is tasked with prototyping advanced chip technologies, as well as workforce development and the training of workers.

The second subgroup under NIST is the National Advanced Packaging Manufacturing Program (NAPMP). And as its name suggests it will focus on packaging and manufacturing of the hardware.

Finally, the funding will also support the creation of three manufacturing institutes also tasked with semiconductor development.

Google declined to tell The Register how much it is willing to spend on this NIST program. "We are not sharing the investment figures for this project," a spokesperson told us.

We're also told by NIST that this effort is separate from the CHIPS Act funding. "This initiative was launched before the CHIPS Act was signed into law, and we do not yet know how it might interact with the programs that are just getting launched," a NIST spokesperson told The Register.

"With cooperative research and development agreements, NIST does not provide funds to collaborators," the spokesperson added, referring to Google in this case. ®

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