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TSMC chips away at the competition with 2nm production set for 2025

World's largest semiconductor contract manufacturer also gives details on 3nm nodes

Taiwanese chip manufacturing behemoth TSMC has given an update on its process technologies, indicating that it is still on track to start production of 2nm chips in 2025, and expanding its 3nm portfolio to include nodes optimized for high performance computing (HPC) and another aimed at automotive applications.

The company showed off its latest technology developments at its North America Technology Symposium 2023 in Santa Clara, shortly after posting its first revenue decline in four years in its Q1 financial results.

TSMC disclosed early details of its next-generation N2 2nm node at last year's symposium, including that it would switch to a nanosheet transistor architecture, where several stacked layers of silicon are completely surrounded by the transistor gate material, instead of the current FinFET designs.

The company said it is making "solid progress" in both yield and performance of N2 silicon, and that it is expecting it to deliver a better than 1.15 times improvement in density over the enhanced N3E node that is due to enter mass production this year. It is also projected to offer a 15 percent speed improvement over N3E at the same power, or up to a 30 percent power reduction at the same speed when it goes into production in 2025.

With its 3nm N3 process now in volume production and the enhanced N3E version coming, TSMC detailed more 3nm nodes that it plans to bring into production.

This expanded lineup will include N3P, which TSMC claims will offer an extra 5 percent more speed than N3E with the same leakage current, or a 5 to 10 percent power reduction at the same speed, plus a slight increase in density. It is due for production in the second half of 2024.

The N3X node will prioritize performance and maximum clock frequencies for HPC applications, and is expected to add another 5 percent speed to that of N3P, but with the same improved chip density as N3P, and set to enter volume production in 2025.

Another part of the 3nm portfolio, N3AE or "Auto Early" allows customers targeting the vehicle market to launch designs this year on the 3nm node, TSMC said, ahead of a fully automotive-qualified N3A process coming in 2025.

TSMC isn't the only semiconductor manufacturer aiming for 2025 to bring 2nm technology into production. Samsung, which beat TSMC to be the first with 3nm, announced last year that it expects to have 2nm chips in mass production by 2025 and 1.4nm silicon by 2027.

Meanwhile, Intel's plans to deliver "five nodes in four years" are expected to see the Santa Clara chip giant start producing silicon using its 20A process in 2024, followed by the 18A process in 2025. These are described as 2nm and 1.8nm nodes, respectively, although there is some dispute over this, with some in the industry saying they are basically 5nm nodes but with 20A "equivalent to" TSMC's 2nm technology.

TSMC also said it is developing N4PRF, a process technology for applications that integrate radio frequency (RF) circuitry, such as Wi-Fi 7 system-on-chip designs. This is expected to offer 1.77 times the logic density and 45 percent less power consumption as the company's existing N6RF technology used for these applications.

The Taiwanese chipmaker is also working on a version of its Chip on Wafer on Substrate (CoWoS) technology aimed at High Bandwidth Memory (HBM), capable of accommodating 12 stacks of memory dies. ®

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