Core blimey, Intel's answer to AMD and Ampere's cloudy chips has 288 of them

And they're all tailored for efficiency

Intel now says its "Sierra Forest" Xeons will actually offer 288 cores, twice as many as previously disclosed, when it launches in the first half of 2024.

When Intel first revealed the efficiency-geared Xeon earlier this year, the company said the chip would be the first to use its Intel 3 (3nm) process node and feature a whopping 144 cores.

While we knew both Sierra Forest and its performance-core equipped sibling Granite Rapids would use a chiplet architecture akin to AMD's, it wasn't clear how many chiplets would be required to achieve these core counts or how they might be arranged. As it turns out, Intel was actually talking about the compute tiles used in Sierra Forest when it came to core count, not the package itself.

On stage at Intel's Innovation this week, CEO Pat Gelsinger revealed the chip would actually feature two compute tiles bringing the total core count to 288, while a pair of IO dies added support for 12 channels of DDR5 or high-speed MCR DRAM DIMMs.

E-core concessions

As with the e-cores we've seen in previous Intel products, which started hitting the market in PC and notebook hardware back in 2021 with the launch of Alder Lake, Sierra Forest won't support simultaneous multi-threading (SMT) or, as they prefer to call it, hyperthreading.

And this isn't the only limitation of Intel's E-core design. Because they're using two distinct microarchitectures for the E-core and P-core processors, certain features on one aren't necessarily available on the other. For example, Sierra Forest lacks several elements, including the chipmaker's Advanced Matrix Extensions for AI acceleration and AVX512 support.

The E-cores will support AVX10, which we looked at earlier this summer. The new spec, which minimally supports AVX2, aims to decouple many core features, like FP16 and brain float 16 mathematics support, which previously were tied to AVX512.

But while you might think jamming 144 cores into a single die might require some concessions, Intel claims that, at a rack level, the chip will deliver about 2.5x more threads at 250 percent higher performance-per-watt compared to its current generation Sapphire Rapids Xeons.

According to Intel Fellow Ronak Singhal, the decision to pursue two discrete core architectures was motivated by a desire to better tailor its Xeon products to cover a broader market.

"As the customers become more diverse in their use cases; as the applications become more diverse, they're really stretching what they want to be able to do. How many cores do they want? What frequency do they want to run out? Do they want to run at high power or low power," he said during a briefing following Tuesday's Innovation keynote. "That span, as it becomes wider and wider, is really hard for a single solution to cover that entire range."

While Intel has yet to test Sierra Forest against the market, the company is already working on the chip's successor, code named Clearwater Forest, which will follow a similar theme but make the jump to Intel's new 18A – 2nm – process tech, which is currently under development.

Better late than never

While Intel may end up holding the core count lead over its rivals when Sierra Forest arrives later next year, the company is still late to the party bringing a many-cored CPU to market.

In fact, in many respects both Intel and AMD are still catching up with Arm-chipmaker Ampere. Introduced in 2020, Ampere's Altra boasted 80, and later, 128 Arm Neoverse cores. Since then nearly every public cloud provider, with the exception of Amazon, has thrown their weight behind the company.

This spring the chipmaker revealed its next-generation processor family called AmpereOne, which see the company move away from Arm's off-the-shelf cores in favor of an in-house design and boost core counts to 196. Though, like Intel's Sierra Forest, the chip doesn't support SMT either, the first of Intel Xeons not to do so.

Since the launch both Oracle and Google have announced plans to deploy the chip in their cloud datacenters.

AMD joined the party in June with the launch of its Bergamo Epycs. The x86-based chip could be had with up to 128 SMT-enabled cores, though AMD does offer versions without multithreading, tailored to cloud and hyperscale workloads.

This approach is quite a bit different than the one employed by Intel's Sierra Forest. While Intel has two distinct micro-architectures for its P and E cores, AMD traded top-end performance to shrink its Zen 4 core by 35 percent while maintaining a common ISA and feature set.

As for whether having a common core architecture will turn out to be a competitive advantage for AMD, or if Intel or Ampere's higher core counts will win out, only time will tell. ®

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