Latest SiFive RISC-V cores aim to boost performance, accelerate AI workloads
Those are some fat vector registers
SiFive today launched a pair of RISC-V CPU cores aimed at high-performance and AI/ML applications.
The Silicon Valley-based biz creates and licenses out a range of RISC-V CPU cores as well as other chip intellectual property to customers to put into their own processors, and also designs its own whole system-on-chips that can be found on its development boards.
The first of these new cores is the Performance P870, a 64-bit out-of-order superscalar processor core that implements the open RISC-V instruction set. It is capable of running Linux, Android, and other compatible OSes, and comes with an IOMMU and hardware support for hypervisors, plus others bits and pieces including SiFive's WorldGuard that performs code and data isolation in system-on-chips.
According to SiFive, its performance cores are intended for applications that require maximum throughput while also minimizing power consumption, such as mobile, edge, datacenter, and automotive markets. The P870 is said to be good for consumer applications, which is perhaps SiFive's way of saying: Please put this in an Android phone.
Compared to its predecessor, the P670, SiFive says the new core offers a 50 percent improvement in performance. This, the chip designer claims, translates into a score of 18 per MHz in the SpecINT2K6 benchmark. And while the chip designer hasn't said just how high the core can clock, SiFive Fellow Brad Burgess suggested we could expect frequencies "well in the 3 GHz range," during a presentation teasing the design at Hot Chips this summer.
Much of the core's performance improvement appears to come from its six-wide out-of-order dispatch, which allows the chip to divvy out instructions more efficiently compared to the older four-wide arrangement on the P670. In terms of vector extensions, not much appears to have changed, with both sporting dual 128-bit units.
As we learned at Hot Chips, SiFive will also offer an automotive version of the chip with a high-degree of redundancy and fault-tolerance built into the cores and systems on chip (SoC) architecture.
SiFive's P870 design can support SoC configurations of upto 32 cores using eight four-core clusters ... Click to enlarge. Source: SiFive
Much like previous SiFive Performance-cores, the P870 is designed to be deployed in clusters that share a pool of L2 cache. This allows the design to support SoCs with up to 32 cores — twice that of its predecessor. During a presentation teasing the core at Hot Chips this year, the company detailed what such a system-on-chip might look like, with eight, four-core clusters, connected by SiFive's multi-cluster interconnect.
However, these clusters don't have to be homogeneous, which means the P870 can be paired with a cluster of slower, efficiency-focused cores like the P470 design, announced last fall, or the chipmaker's Intelligence family of vector-optimized cores.
For example, NASA's High-Performance Spaceflight Computer (HPSC) features eight Intelligence X280 cores in addition to four general purpose RISC-V CPU cores.
So you like big vectors?
The second core design announced Wednesday is the successor to SiFive's X280 core, which its calling the X390.
While cores like the P870 do support vector instructions in hardware, SiFive's Intelligence series is specifically designed to accelerate large-vector instructions commonly used in AI and machine learning use cases.
For example, the X280 we mentioned earlier supports 512-bit wide vector registers. You can think of these cores in the same vein as Intel or AMD's AVX-512 instructions, but rather than build them into the general purpose core, SiFive has implemented them as a standalone one.
The newly announced X390 claims to quadruple the vector performance of its predecessor. This was achieved by doubling the vector length. The core features support for 1024-bit long vector registers (VLEN) with 512-bit long data paths (DLEN).
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SiFive didn't disclose the supported data types ahead of today's launch. However, we do know that the X280 design supported [PDF] INT8, INT16, INT32, FP16, FP32, and FP64 in addition to Q8.8 to Q15 fixed-point data types, making it widely applicable to a variety of AI and ML workloads. We've asked SiFive if the new design adds support for any other data types.
The core can be had with either single or dual vector arithmetic logic units and comes equipped with SiFive's Vector Coprocessor Interface Extension (VCIX), which provides an avenue for customers to implement their own vector instructions or acceleration hardware. So, if a customer wants to do something more specialized with the cores, they can.
Trouble on the horizon?
The launch of SiFive's latest core designs comes less than a week after a bipartisan group of US lawmakers called for the Biden administration to extend export controls on semiconductors to China to include the open RISC-V ISA.
The calls prompted RISC-V International CEO Calista Redmond to pen a memo warning politicians that such action was likely to result in the development of incompatible solutions and stifle innovation.
Over the past few years, we've seen a number of RISC-V-based chips announced from Chinese outfits. Last winter, the People's Republic of China reportedly tapped Alibaba and Tencent to design RISC-V chips to help insulate itself from US sanctions.
However, restrictions on the export of semiconductor intellectual property aren't new. In a pre-IPO regulatory filing, Arm disclosed that its more powerful Neoverse cores were barred from sale in China without special licenses. ®