Standardization could open door to third-party chiplets in AMD designs

Domain-specific accelerators are 'essential to progress' it claims, and a chiplet ecosystem is one way forward

Video Future AMD processors could feature domain-specific accelerators – even some created by third parties, according to senior execs at the chip shop.

Speaking with AMD CTO Mark Papermaster in a video released Wednesday, senior vice president Sam Naffziger stressed the importance of chiplet standardization. You can watch all 25 minutes below.

Youtube Video

"Domain-specific accelerators, that's the best way to have the best performance per watt per dollar. So it is absolutely essential to progress. You can't afford to do a specific product for each one of these domains, so what we can do is have a chiplet ecosystem – a library essentially," Naffziger explained.

He was referring to Universal Chiplet Interconnect Express (UCIe) – an open standard for chiplet communications that, since its creation in early 2022, has won wide support from key industry players including AMD, Arm, Intel, and Nvidia, and many other smaller names too.

AMD has been at the forefront of chiplet architectures since the launch of its first-gen Ryzen and Epyc processors in 2017. Since then, the House of Zen's chiplet library has evolved to include multiple compute, I/O, and graphics dies, which it combines and packages in its consumer and datacenter processors.

An example of this approach can be found in AMD's Instinct MI300A APUs, launched in December 2023 and packing 13 individual chiplets – four I/O dies, six GPU dies, and three CPU dies – along with eight stacks of HBM3 memory.

Naffziger suggested that in the future, standards like UCIe could see chiplets built by third parties make their way into AMD packages. He mentioned silicon photonic interconnects – a tech that may ease bandwidth bottlenecks – as having potential to bring third-party chiplets into AMD products.

Naffziger argued that without a low-power die-to-die interconnect, the technology isn't viable.

"You bolt optical on because you want massive bandwidth. So, you need low-energy per bit for that to make sense and in-package chiplets are the way to get the lowest energy interfaces," he explained, adding that he thinks that the move to co-packaged optics is "coming."

To this end, several silicon photonics startups are already pushing products that do just that. For example, Ayar Labs has developed a UCIe-compatible photonics chiplet that was integrated into a prototype graph-analytics accelerator built by Intel last year.

Whether third-party chiplets – photonics or otherwise – make their way into AMD products remains to be seen. As we've previously reported, standardization is just one of many challenges that needs to be overcome to allow heterogeneous multi-die chips. We've asked AMD for more information on its chiplet strategy, and will let you know if we hear anything back.

AMD has made its chiplets available to rival chipmakers before. Intel's Kaby Lake-G parts, launched in 2017, featured Chipzilla's 8th-gen cores along with AMD's RX Vega GPU. The part recently resurfaced in a NAS board from Topton. ®

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