TSMC says first 1.6nm chips coming in 2026

Watch out Intel ... Angstrom-class A16 with Super Rail backside power tech incoming

Semiconductor giant TSMC has disclosed details of a process technology called A16 that could be delivering the first 1.6nm chips for customers by 2026.

The Taiwan-based contract manufacturing titan revealed its latest advances in semiconductor process, advanced packaging, and 3D chip technology at the company's North America Technology Symposium 2024 in Santa Clara this week.

The headline act at the event was A16, the next semiconductor process technology on its roadmap. TSMC said this is planned for production in 2026, and that silicon from it will provide an 8-10 percent speed improvement over its N2P process, itself a refined version of the company's 2nm technology due to start production next year.

A16 has been reported to be a 1.6nm process node, but TSMC did not explicitly identify it as such at first. We asked for clarification, and the company told us that the A stands for angstroms, and as there are 10 angstroms in 1nm, A16 is therefore a 1.6nm process – but TSMC does not refer to it as such.

TSMC disclosed that A16 will combine its nanosheet transistor design, set to be introduced on 2nm, with Super Power Rail technology. The latter is the company's implementation of the charmingly named backside power architecture, where tracks that carry the power to transistors are moved to the reverse side of the silicon to make way for more signal tracks. Intel revealed its use of the technique last year.

This will offer improved logic density and performance by dedicating front-side routing to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks, TSMC said.

According to Reuters, TSMC indicated that it does not need ASML's latest High NA EUV photolithography machines in order to produce chips with its A16 process. It had been suggested by some in the industry that Intel would be able to steal a march on TSMC because it was the first chipmaker to receive one of these.


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For the company's upcoming N2 2nm process node, TSMC announced a design optimization technique it calls NanoFlex. This simply provides chip designers with flexibility in standard cell building blocks, allowing them to tune a combination of short cells for greater power efficiency and tall cells for maximum performance to hit the best power, performance, and area trade-offs for their application.

The semiconductor supremo also updated its 4nm process technology with N4C. This adds area-efficient design rules that are compatible with its popular N4P process, but which will deliver an 8.5 percent die cost reduction for "value-tier" products, TSMC claims. This is scheduled for volume production in 2025.

In packaging technology, TSMC declared that its first System-on-Wafer (SoW) offering is already in production. This enables a large array of dies on a 300 mm wafer to form a single system, boosting compute power while occupying far less space.

The company said that a Chip-on-Wafer version is slated to be ready for 2027 that will use its Chip-on-Wafer-on-Substrate (CoWoS) technology, and claimed this will enable integration of High Bandwidth Memory (HBM) and other components to create a powerful wafer-level system with compute power comparable to an entire datacenter server rack.

TSMC also said it is developing Compact Universal Photonic Engine (COUPE) technology for high-speed interconnects, citing AI as an application that will need this. The technology will use chip stacking to mount an electrical die on top of a photonic die, and the company plans to qualify COUPE for small form factor pluggable modules in 2025, followed by integration into CoWoS packaging the following year.

"At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world's most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world," TSMC CEO C C Wei said in a statement.

TSMC reported revenue up year-on-year for the first quarter of 2024 earlier this month, beating expectations, and said it anticipated that demand for AI-capable PCs and datacenter kit will drive higher sales of the silicon it produces this year. ®

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