SiPearl updates specs for Rhea1 processor set to power Europe's exascale dreams

More cores, more memory, more delays

ISC Chip designer SiPearl has issued updated specs for its Rhea1 processor that will power Europe's first exascale system and is working with Samsung to integrate high-bandwidth memory (HBM) into its design.

SiPearl was picked by the European Processor Initiative (EPI) to develop an Arm-based processor to drive European supercomputers, particularly the Jupiter system, which is slated to be the region's first exascale project.

At the ISC 2024 high-performance computing event, SiPearl disclosed that its first-generation Rhea1 product will feature 80 of Arm's Neoverse V1 cores. Each core includes a pair of 256-bit Scalable Vector Extension (SVE) units to boost its vector processing capabilities, useful for crunching vector and matrix calculations for supercomputing workloads.

Rhea was previously slated to feature 72 Neoverse cores, but as rivals such as Nvidia's Grace CPU have emerged with 72 Neoverse cores, perhaps SiPearl felt it had to go a bit further. In response to our queries, a SiPearl spokesperson claimed the company had always intended for it to have 80 cores.

Each Rhea1 processor will also feature four stacks of HBM to provide a balanced solution ideal for HPC, big data, and AI Inference applications that are often memory bandwidth bound, SiPearl said. HBM achieves higher bandwidth by stacking memory dies atop one another inside the same chip package as the CPU or GPU they are connected to.

SiPearl told us that for this first-generation processor, the HBM version used will be HBM2e. This is despite newer HBM3 and HBM3e versions being available, and HBM4 now under development.

The company said it has entered a partnership with Samsung Electronics, currently the biggest memory manufacturer, to equip the Rhea series of processors with HBM. Samsung has indicated it expects HBM4 to be introduced by 2025, which is the same year that SiPearl now intends to have first samples of Rhea1 available with HBM2e.

In addition to HBM in the chip package, each Rhea1 processor will have four DDR5 external memory interfaces supporting two DIMMs per channel, with IO being delivered through 104 lanes of PCIe Gen 5, divided up into 6 x16 lanes plus 2 x4 lanes.

Internally, the Rhea1 will also make use of Arm's Neoverse CMN-700 Coherent Mesh Network on Chip (NoC) to interconnect its various compute and IO elements.

According to SiPearl, Rhea1 is set to deliver "extraordinary performance and energy-efficiency" with an "unrivaled byte-per-flop ratio" thanks to its memory capacity and the high bandwidth of in-package HBM.

"Rhea1 will fulfil the mission entrusted by EuroHPC JU and the European Processor Initiative consortium: to bring dedicated high-performance microprocessor technologies back to Europe," SiPearl CEO and founder Philippe Notton said in a statement.

He claimed that Rhea1 will be a "world-class microprocessor" for HPC and AI inference, and a great alternative to existing solutions for inference workloads at lower cost while offering higher flexibility to model changes.

However, Rhea1 is already late. It was supposed to have been available in 2022, but SiPearl then said that the first silicon, to be manufactured by TSMC, would appear in 2023. Now it is looking at 2025. ®

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