CHERI Alliance formed to promote memory security tech ... but where's Arm?

Academic-industry project takes next step as key promoter chip designer licks its wounds

Updated A group of technology organizations has formed the CHERI Alliance CIC (Community Interest Company) to promote industry adoption of the security technology focused on memory access.

We will also work with the industry to reach common ground when it comes to specifications for how to implement CHERI

The CHERI Alliance hopes to drive the adoption of enhanced security, with its initial members comprising the FreeBSD Foundation, security consultancy outfits Capabilities Limited and SCI Semiconductor, chip designers Codasip and lowRISC, and the University of Cambridge, which is one of the prime movers behind the technology.

CHERI, or Capability Hardware Enhanced RISC Instructions, comprises instruction-set extensions that implement fine-grained memory protections in CPU hardware. This technology aims to combat common vulnerabilities such as buffer overflows and the misuse of pointers via use-after-free errors.

Arm headquarters in Silicon Valley

How Arm popped CHERI architecture into Morello Program hardware


It is the result of a research project between the University of Cambridge and US-based research institute SRI International. Because it can be applied selectively to critical functions and requires almost negligible software modifications, the security of existing applications can be enhanced with minimal effort, if the hardware support is in place.

According to the CHERI Alliance, its governing board is set to include representatives from industry as well as academia, with the aim of galvanizing industry leaders, system developers, users, and security experts to drive and promote CHERI as an efficient security standard.

"As noted by the White House in a recent report on a path toward secure and measurable software, hardware support is critical to robust and efficient memory safety. Compiling software to run on CHERI enhanced processors guarantees very strong memory safety that an attacker cannot bypass," University of Cambridge Professor Simon Moore said in a statement.

However, one notable name missing from the list of CHERI Alliance initial members is chip designer Arm, which has also played a key role in the development and promotion of CHERI.

This is particularly ironic, given the news this week that an existing hardware security feature introduced by Arm called Memory Tagging Extensions (MTE) can be bypassed in certain circumstances.

Back in 2022, Arm produced prototype chips that implemented CHERI functionality into the Armv8.2-A instruction set architecture (ISA) as part of the company's Morello research program. It shipped prototype boards built with the chips for testing by developers and security specialists.

The company also discussed in detail the Morello Program and how it implements the CHERI architecture at the Hot Chips conference later the same year.

We asked Arm and the CHERI Alliance about its absence and whether the company planned to join in future.

A spokesperson for the CHERI Alliance told us it could not comment about Arm, but said that the organization was ISA agnostic and would welcome Arm and any other ISA vendor.

When it comes to its plans for driving broader industry adoption of CHERI, the alliance said it is "working on several levels."

"Creating awareness is key, not only among industry players but also with legislators and open-source communities," the spokesperson told us.

"We will also work with the industry to reach common ground when it comes to specifications for how to implement CHERI, provide a networking platform to encourage collaboration, speed up projects by leveraging academic-industry partnerships, and find how to fill the gaps and drive user requirements through the value chain."

Perhaps not surprisingly, much of the CHERI effort now seems to have focused around the RISC-V open ISA, with Codasip and lowRISC both involved in RISC-V design work. The University of Cambridge also last year announced CHERI ISAv9 [PDF], which replaces CHERI-MIPS with CHERI-RISC-V as the primary reference architecture.

The CHERI Alliance is set to formally launch in September, but is already accepting new member applications. Interested parties can contact the alliance here. ®

Updated at 13.06 UTC on June 19, 2024, to add:

Following publication of this article, an Arm spokesperson sent us the following statement:

"Arm has chosen not to participate in the CHERI Alliance at this time. Morello has been a successful 5 year research project, but throughout the prototyping testing process we have learned a great deal about the CHERI use cases and believe that the initial opportunities for a wide commercial deployment are relatively limited.

"We are continuing to work with partners, using the Morello platform, to establish a business case for Arm products which incorporate the CHERI technology, and are providing support through engineering and funding."

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