PCIe 7.0 specs finalized at 512 GBps bandwidth, PCIe 8.0 in the pipeline

Work on next gen already underway, while bandwidth needs for datacenters just keep rising

The PCI Special Interest Group (PIC-SIG) just released official specs for PCIe 7.0, doubling the bandwidth again for high-performance kit such as network cards, while hinting that PCIe 8.0 may not achieve the same.

The headline figures in this release are a doubling of the bandwidth to deliver a raw bit rate of 128 GTps (gigatransfers per second). This translates as up to 512 GBps bi-directionally in an x16 lane configuration.

PCIe 6.0, which was finalized in 2022, supported 64 GTps for up to 256 GBps with 16 lanes.

This increase in capacity is needed for throughput-heavy devices such as 800 Gbps Ethernet adapters and data-intensive applications, including High Performance Computing (HPC) and machine learning. But as with previous versions, there tends to be a lag of at least 12-18 months between the release of the final specifications and products hitting the market.

For example, few PCIe 6.0 devices have so far hit the market. Micron last year trumpeted the industry's first PCIe Gen6 SSD, claiming it was capable of exceeding 26 GBps for sequential reads in tests. This has been spotted in the wild at trade shows, but only as a demo unit.

As the industry body overseeing the standard, the PCI-SIG has now given out the PCE 7.0 specifications to its member organizations. Much of the detail was already known from draft versions issued over the past year or so.

"PCIe technology has served as the high-bandwidth, low-latency IO interconnect of choice for over two decades and we are pleased to announce the release of the PCIe 7.0 specification, which continues our long-standing tradition of doubling the IO bandwidth every three years," said PCI-SIG president and chairperson Al Yanes.

The PCI-SIG also announced specifications providing an industry standard way to implement PCIe using optical fiber links for the first time.

This comes in the shape of an Optical Aware Retimer Engineering Change Notice (ECN) that amends the PCIe 6.4 specs and the new PCIe 7.0 specs to include a PCIe retimer, a component that regenerates and re-times the data signal to avoid degradation when extending a link over a relatively long distance, across racks, for example.

"We saw a need for an industry standard optical interconnect based on PCIe technology and the Optical Aware Retimer ECN is the first step to add a modular optical solution," Yanes said.

Initial adoption of the tech will likely be for datacenter applications like AI/ML and cloud, he added, but as it becomes more widely available over time, there could well be many use cases across many market segments.

Pathfinding for a PCIe 8.0 specification has already begun, in order to continue to meet the inexorable increase in bandwidth requirements seen in the datacenter.

However, at a press conference to announce the 7.0 specs at the PCI-SIG Developers Conference in Santa Clara, Yanes said the PCI-SIG could not guarantee the next release would continue the tradition of doubling the bandwidth in each new generation.

"We are hoping to double again, but I do not want to make any definitive claims at the moment," he said.

If it proves possible, then PCIe 8.0 can be expected to hit a bandwidth of a terabyte per second when using 16 lanes.

In response to a question, Yanes said he did not believe that PCIe 8.0 would end up being implemented as a purely optical interface.

"We believe we can do electrical and optical. We do not think it is just going to be optical," he stated. ®