Edge + IoT

Android 10 ported to homegrown multi-core RISC-V system-on-chip by Alibaba biz, source code released

AOSP effort could help bring GUIs to industrial, IoT, embedded gear

Alibaba-owned T-Head Semiconductor says it has ported Android 10 to its own RISC-V chips, highlighting increased momentum for the open-source instruction set architecture (ISA) against proprietary alternatives.

T-Head (also known as Pintouge, which translates to "honey badger") this week demonstrated the open-source base of Android – known as AOSP – running on a prototype board powered by its own silicon. The configuration consists of three 64-bit RISC-V XuanTie C910 cores, each clocked at 1.2GHz with one supporting 128-bit vector instructions, all paired with an unspecified GPU core.

T-Head isn't the only outfit interested in bringing Android to RISC-V. Last November, PLTC Labs, part of the Chinese Academy of Sciences, managed to get the Android kernel to boot in a virtualized environment. This wasn't a full system, however, containing just the Android shell and not much else.

This time around, we're shown something that more resembles a typical Android experience, with a full GUI and touchscreen interactions. And while this is merely a proof of concept, it could set the stage for future development by device makers and chip designers alike.

RISC-V is a royalty-free, open-source ISA. Since it was introduced in the early 2010s, interest in the tech has grown, particularly in China and India, where it is seen as a way to reduce their dependence on foreign technology suppliers. While organizations are free to implement the RISC-V specifications in CPU cores for their own chips with or without releasing the source code of those designs, there are a number of blueprints available as open source or for a licensing fee.

For Middle Kingdom businesses wary of falling afoul of US sanctions, RISC-V is something of an insurance policy or escape route – albeit one that still needs time to mature.

Speaking to El Reg, Gartner VP analyst Alan Priestly described the porting of Android 10 as an "interesting development," and could be useful for adding graphical user interfaces to RISC-V-powered IoT and embedded systems.

"Many embedded/industrial system leverage Android to provide graphical user interfaces and Android apps are written in Java (as is a lot of Android itself) so the apps are processor ISA agnostic and would be easily ported to RISC-V based processors," Priestly said.

Beagleboard peeps tease dual-core 64-bit RISC-V computer with GPU, AI acceleration, more for under 100 quid


"In the near term, use of RISC-V is a good option for many vendors developing low-cost embedded chips as there are no licensing or royalty fees associated with RISC-V IP (unless they want to use the RISC-V logo) and having Android support provides a relatively lightweight OS with good app development support."

On the mobile front, it might take some time for RISC-V to have a real impact. Compatibility with graphically intensive apps, like games, will be a problem as many game engines are written natively in C and C++, and specifically target the Arm architecture. It would also require some upfront investment from vendors to match incumbent silicon in performance and power efficiency.

"I'm not sure I have seen any vendor going down this route, but it's always a possibility if Nvidia closes its acquisition of Arm and a vendor has concerns working with a major competitor," Priestly added.

Geoff Blaber, VP of Research at CCS Insight, largely agreed, saying: "RISC-V has seen significant momentum in adoption, particularly in industrial IoT. Replacing Arm as a 'big core' in a smartphone is a little way off but this porting of Android is a clear indication of where RISC-V is heading.

"RISC-V already has a role in smartphones today in terms microcontrollers. Long term it's a clear challenge to Arm, particularly in industrial IoT. Should Arm end up part of Nvidia, this will undoubtedly represent another catalyst for growth."

Source code for T-Head's AOSP 10 port, as well as instructions on how to run it in a Qemu-emulated environment, can be found on its GitHub page. ®

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