Chip design is a RISC-y business: Codasip puts itself up for sale
R&D teams are 'separable' says biz, which is open to offers for parts or the whole
European RISC-V biz Codasip has put itself up for sale, citing an expression of interest during a recent funding round, and is now openly touting for buyers.
The Munich-based developer of RISC-V chips and electronic design tools said it has officially kicked off the process today, July 1, and expects it to be complete within the next three months, which may indicate that a buyer is already in place.
However, the firm said its board is open to considering offers to acquire the entire company, or even portions.
Codasip is reported to have an estimated annual revenue of $88.7 million, which would make it one of the larger chip designers in the RISC-V processor ecosystem. Ventana Micro Systems has an estimated revenue of $37.4 million, while SiFive was expecting to make about $60 million last year.
The company says it has business units targeting four key product areas, with "separable" research and development teams, presumably for the benefit of anyone thinking of snapping one up.
It has a portfolio of RISC-V designs for application and embedded processor chips; a second portfolio of RISC-V processors that implements the CHERI security architecture that addresses memory safety violations, along with complementary software; and the Studio electronic design automation (EDA) toolset for developing and customizing processors.
Finally, there is another portfolio of high-performance application processors that is being developed using European Union funding, under the Digital Autonomy with RISC-V in Europe (DARE) project.
In fact, Codasip seems to place a certain amount of emphasis on the grants and equity funding it has from various EU bodies in its declaration that it is for sale.
These currently total over €119 million ($140 million), most of which is still to be received by the company, while estimates for the follow-on phases of the grants will total a further €210 million ($248 million) for a total of €329 million ($388 million). The company also claims it is part of new consortiums and projects that can bring in an additional €51 million ($60 million) or more in future financing.
These substantial funds are transferable to a buyer under reasonable terms, Codasip says.
In response to questions from The Register, the firm said it could not divulge who expressed interest in acquiring it because of legal reasons.
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However, chief product officer Jamie Broome told us that there would likely be two outcomes of the sale.
"A more vertical player will use the Codasip technology to rapidly build their own RISC-V portfolio internally, especially with the ease of customization we enable. Then the second is under an IP licensing or subscription model more aligned to what we offer today, but critically with the investment to achieve the scale needed. The latter is especially key in Europe," he said.
While RISC-V has sparked a certain amount of interest because it is an open instruction set that anyone can use to make a processor, the path to building a successful business around it has not always been smooth.
Two years ago, SiFive laid off 20 percent of its engineers and other staff in a dramatic restructuring, while Intel ditched its own initiative, the RISC-V Pathfinder, earlier the same year. Imagination Technologies in the UK also shut down its development of RISC-V processor cores earlier this year to focus on GPU and AI products instead.
"First and foremost, being a CPU designer is an expensive business, so long term funding is essential – if market acceptance is low, revenues are not immediately forthcoming," commented Andrew Buss, Senior Research Director for IDC in EMEA.
"We've seen this with Arm based CPUs. In the datacenter, Arm has not seen much significant traction, outside of hyperscalers designing their own offerings. As a result of this weak demand, Ampere was recently acquired by Softbank," he added.
"Ecosystems are always a challenge, and the software people (and particularly kernel level people) seem to have a view that RISC-V does not move the needle forward in terms of instruction set architecture, but makes many of the mistakes of the past." ®