RISC-V

Created by Team Register //

Mon 18 Oct 2021

RISC-V is an open royalty-free instruction set architecture for general purpose CPU cores. RISC-V International sets and publishes the specification of this architecture, and chip designers are free to implement it in their components.

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RISC-V

Open ISA champ SiFive leaps aboard Nvidia's proprietary interconnect bandwagon

India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64

Qualcomm takes RISC on Arm alternative with Ventana acquisition

Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole

HPC won't be an x86 monoculture forever – and it's starting to show

Bolt Graphics unveils Zeus GPU built on RISC-V and path tracing tech

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Chip designer SiFive aims to cram more RISC-V cores into AI chips

PinePhone Pro canned in pursuit of RISC-V business

Torvalds blasts tardy kernel dev: Your 'garbage' RISC-V patches are 'making the world worse'

Nvidia extends CUDA support to RISC-V just in time for next wave of Chinese CPUs

Chipmaker GlobalFoundries acquires chip designer MIPS

Chip design is a RISC-y business: Codasip puts itself up for sale

China claims breakthroughs in classical and quantum computers

Chimera Linux ghosts RISC-V because there's no time for sluggish hardware

Do you DARE? Europe bets once again on RISC-V for supercomputing sovereignty

As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA

NASA’s radiation tolerant computer lives up to its name after surviving Van Allen belts

US adds Chinese RISC-V player that TSMC suspected of helping build Huawei GPUs to risky company register

Chinese RISC-V project teases 2025 debut of freely licensed advanced chip design

RISC-V is making moves, but it has work to do if it wants to hit the mainstream

RISC-V's AI champion just scored $693M cash infusion

Framework laptops get modular makeover with RISC-V main board

AI chip startup Tenstorrent to train Japan's engineers in $50M government deal

RISC-V reaches milestone with RVA23 profile ratification

Codasip opens up SDK for CHERI protection on RISC-V chips

SiFive launches early access for Premier P550 RISC-V developer board

Bending the rules with flexible non-silicon 32-bit RISC-V chip

Xen to RISC-V port progresses with foundational efforts

SiFive expands from RISC-V cores for AI chips to designing its own full-fat accelerator

Tenstorrent's Blackhole chips boast 768 RISC-V cores and almost as many FLOPS

SiFive offers potential Neoverse N2 rival – the P870-D RISC-V core for datacenters

Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle

Raspberry Pi Pico 2 lands with (drum roll) RISC-V cores

Faulty instructions in Alibaba's T-Head C910 RISC-V CPUs blow away all security

Linux kernel 6.10 arrives with punched-up hardware support

World's first RISC-V laptop with Ubuntu preloaded touts AI smarts and octa-core chip

Why RISC-V must get its messaging right on open standard vs open source

Google pulls RISC-V support from generic Android kernel

US government reportedly ponders crimping China's use of RISC-V

RISC-V AI chip upstart Rivos plans to undercut Nvidia, helped by a quarter-billion in VC lucre

SiFive is back with another 64-bit RISC-V dev board – hopefully

Imagination licenses RISC-V CPU cores for smart TVs, IoT, embedded stuff

Chinese schools testing 10,000 locally made RISC-V-ish PCs

Scaleway shows off its new RISC-V devices at Kubecon

RISC-V PCIe 5 SSD controller for the rest of us hits 14GB/s

Alibaba's research arm promises server-class RISC-V processor due this year

Leaked docs hint Google may use SiFive RISC-V cores in next-gen TPUs

French cloud Scaleway starts renting Alibaba's RISC-V SoC

India’s homebrew RISC-V CPU goes on sale in new development board

MIPS snags top SiFive brains to amp up RISC-V business

Ventana bumps performance on Veyron RISC-V silicon to surely speed up servers

Synopsys joins RISC-V party with trio of embedded core designs

Hardware hacker: Walling off China from RISC-V ain't such a great idea, Mr President

Arm grabs a slice of Raspberry Pi to sweeten relationship with IoT devs

Google formally gets to work on Android on RISC-V

RISC-V champ SiFive confirms it's laying off 1 in 5 workers

Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm

India courts IBM, Intel, and Tower for chip partnerships - all in one day

Google and Qualcomm to bring RISC-V to the wrist in next-gen wearable platform

Latest SiFive RISC-V cores aim to boost performance, accelerate AI workloads

RISC-V org claims export restrictions would stifle innovation

Boffins propose RISC-V microcontroller to power cubesats

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