RISC-V

Created by Team Register //

Mon 18 Oct 2021

RISC-V is an open royalty-free instruction set architecture for general purpose CPU cores. RISC-V International sets and publishes the specification of this architecture, and chip designers are free to implement it in their components.

RISC-V

Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance

Chinese chip designers hope to topple Arm's Cortex-A76 with XiangShan RISC-V design

Deep neural networks... IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI

Intel made $2bn+ takeover offer for RISC-V chip darling SiFive – report

RISC-V boffins lay out a plan for bringing the architecture to high-performance computing

China's ISCAS to build 2,000 RISC-V laptops by the end of 2022 as nation seeks to cut reliance on Arm, Intel chips

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'A fair amount of stuff, all over the place': Torvalds closes merge window for Linux 5.13 with support for Apple M1

What links AMD CPU guru Jim Keller, an AI chip upstart, and SiFive? This vector-crunching 64-bit RISC-V processor

Android 10 ported to homegrown multi-core RISC-V system-on-chip by Alibaba biz, source code released

Beagleboard peeps tease dual-core 64-bit RISC-V computer with GPU, AI acceleration, more for $119

SiFive inches closer to offering a true RISC-V PC: Latest five-core dev board includes PCIe, SSD interfaces

India shows off new home-grown CPU – but at 100MHz, 32-bit and 180nm, it’s a bit of a clunker

What did they do – twist his Arm? Ex-Qualcomm senior veep joins SiFive as CEO, RISC-V PC for devs teased

Nvidia says regulators will be 'very supportive' of $40bn Arm buy despite concerns about chip designer's independence

India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit

Psst, you want us to design you an Arm chip? 'Cause we can do that, says RISC-V processor darling SiFive

If you wanna make your own open-source chip, just Google it. Literally. Web giant says it'll fab them for free

Arm dumps risk for CISC – Chip Indies Skip Costs: Early-stage startups can pay $0 to access CPU, GPU blueprints

Chips that pass in the night: How risky is RISC-V to Arm, Intel and the others? Very

RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G...

RISC-V business: Tech foundation moving to Switzerland because of geopolitical concerns

Cambridge boffins and Google unveil open-source OpenTitan chip – because you never know who you can trust

Talk about a calculated RISC: If you think you can do a better job than Arm at designing CPUs, now's your chance

Alibaba sketches world's 'fastest' 'open-source' RISC-V processor yet: 16 cores, 64-bit, 2.5GHz, 12nm, out-of-order exec

On the first day of Christmas, MIPS sent to me: An open-source-ish alternative to RISC-V

Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs

Linux lobby org joins with RISC-V bods to promote open chip spec

Need a modest Arm Cortex-A CPU in your custom chip? Just apply online. Plus $125,000

Arms race: SiFive, Hex Five build code safe houses for RISC-V chips

Up in arms! Arm kills off its anti-RISC-V smear site after own staff revolt

Brains behind seL4 secure microkernel begin RISC-V chip port

WD to move all its stuff to RISC-V processors, build some kind of super data-wrangling stack