Updated Chips will be as hot as nuclear reactors by the end of the decade... and as hot as the surface of the sun by 2015, if they continue on their current design path, according to Pat Gelsinger, Intel's architecture chief.
Obviously something's got to give if these thermal problems can't be solved: which he characterises as "no longer business as usual".
Interestingly, two of his suggested remedies for beating the heat and power consumption issues are borrowed from Chipzilla's competitors. These are: SMT which will be used in future revs of Alpha processor; and the multiple cores on a die approach adopted by IBM for POWER4 and Sun Microsystems for its MAJC processor. The former may already be supported, according to some reports, in Intel's Foster chip: it's Pentium 4 for servers. And diligent Reg readers have pointed out that we first discussed this here.
Kicking Pat delivered the keynote at the IEEE's International Solid State Circuits conference, which draws over 3,000 semiconducor engineers to San Francisco.
The nub of his presentation is this. Moore's law will remain true for the next ten years: but the thermal properties and power requirements of future chips conforming Moore's rule of thumb will be unsellable, unless design approaches are radically revised.
"No one," as Gelsinger puts it,"wants to carry a nuclear reactor in their laptop onto a plane". He acknowledges that Intel has contributed to the general power and thermal issues by sacrificing efficiency for performance in the push for higher frequencies, by designing deeper pipelines, with less gates per pipeline. "We make big fat transistors to drive up the frequency."
"I don't think these decisions were bad... but I don't think we know to cool a 5000W chip." Keeping the die size constant, or maintaining voltage as a constant for future generations of chips are inadequate answers, he says.
Engineers will have to design their way past thermal issues. Heat isn't the only issue: memory latencies are bad, and getting worse, with 1000 clock cycle penalty for going out to main memory after a cache miss "a truly whopping number," according to Gelsinger, momentarily slipping into Reg-Speak. "It's a fairly dire picture."
Rotten to the Core
There are of course a host of new design approaches the industry can take. Gelsinger says Intel has been checking out multi-threading processors that look like two or more CPUs to software applications.
Compaq calls this SMT, or simultaneous multi-threading, and it will appear in EV8 Alphas next year. With SMT, the software sees a 4way SMP box; and it will supersede earlier Alphas for Compaq's VMS and Tru64 lines, and replace the MIPS processors used in its Himalaya servers today.
Such a model adds maybe 10 per cent to the logic on a chip, but adds under 10 per cemt thermal cost, compared to a 2x increase in heat and power for conventional revs, according to Intel estimates cited by Gelsinger. It also provides a cheap SMP. But the problem is, he says, is that few applications use pervasive multithreading (BeOS users will disagree, but alas, there aren't really that many of us).
The multiple cores on a die approach of MAJC and POWER4 also offered benefits, he says. Like SMT, it allowa the chip to throttle back performance, rather than design around worst-case, flat out, all-pipelines-full scenarios, which hardly ever happen. Fancy that, we thought.
Other approaches are to offload specific computational tasks onto a dedicated integrated DSP or special instruction set, such as SSE2.
But some questions remain. Is Foster's Jackson Technology really SMT, or an aid to help SMP threads?
If it's SMT, then what will the Alpha design team over in Massachusetts make of Intel's Damascene conversion? Of course, when the Great Satan of Walk-In Wardrobes settled DEC's Alpha-Pentium lawsuit, Palmer worked out some pretty complex intellectual property sharing and manufacturing agreements with Grove.
Does this now allow Intel first dibs on SMT? And if so, what's in it for Big Q? ®