WD is firing up an early production run of its 512Gbit 64-layer 3D NAND chip at its Yokkaichi, Japan, foundry, with its partner Toshiba. The silicon uses a triple-level cell (TLC) flash design, which stores three bits per cell.
Progressing from this pilot job to mass manufacturing will take at least six months, so don't expect a final product to arrive until the second half of 2017.
Meanwhile, Micron is plugging away with 64-layer 3D NAND: it says it's working on a 256Gbit chip with a 59mm2 surface area, which is claimed to be the smallest 64-layer 3D NAND chip. Micron boasts its die has a density of about “4.3Gb/mm2 (>25 per cent more die per wafer relative to competitor’s 64 Tier 3D NAND)".
If you're getting deja vu, that's understandable: back in July 2016, WD claimed it was starting 64-layer 3D NAND pilot production using its BiCS3 technology, as it is now in 2017. What’s different?
Those 2016 chips had a capacity of 256Gbit, half that of the parts announced today. Last year, WD said it would double the capacity of its 3D NAND, which it has now done. WD’s earlier BiCS2 3D NAND chips had 48 layers and a 256Gbit capacity in a 105mm2 surface area.
Back in July 2016, we reported that meaningful commercial volumes of BiCS3 products should start in the first half of 2017. There appears to have been a six-month delay while WD doubled the capacity of its 3D NAND technology.
WD’s executive veep for memory technology Dr Siva Sivaram gushed: “This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data centre applications.”
Meanwhile, SK Hynix is working on a 72-layer part, and back in July, Samsung claimed it would have its 64-layer 3D NAND chips in production before WD and Toshiba.
A thought: if WD and Toshiba can produce a 512Gbit TLC chip, could the pair produce a 682Gbit chip using QLC (that's four bits per cell)? WD staff will present a “512Gb 3b/cell flash memory on 64-Word-Line-Layer BiCS Technology” on Tuesday, February 7 at 8.30am at the 2017 IEEE International Solid-State Circuits Conference in San Francisco’s Marriott Marquis Hotel. ®